Electronic Design

Hot Product

Starting life as a design services organization, ReShape Inc. has brought its secret sauce to market in the form of the GDS Builder tool. This hierarchical physical design system coaxes the tools within an existing back-end physical flow to take a design from netlist to verified GDSII in two weeks or less, with layout quality akin to that derived using flat methodologies. Design respins can take less than 24 hours with remarkably repeatable results.

GDS Builder leans on two key elements to deliver such fast turnarounds. First, it constructs chips hierarchically, partitioning the design into blocks that can be built in parallel on fast, low-cost Linux servers. Second, it speeds up the verification process by bottling expertise in driving the user's existing analysis tools.

The tool's hierarchical approach generates extremely dense layouts that hinge on channel-less block abutment. The company's Design Aware technology automatically optimizes difficult tasks for hierarchical flows, including block pin assignment, global repeater insertion, and power distribution. It uses a given chip's previous builds as the basis for optimizations, exploiting design iteration.

GDS Builder supports Synopsys, Mentor Graphics, and Cadence tools. Call ReShape for pricing.

ReShape Inc.
(650) 230-3200

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