As process technology shrinks beyond the 45-nm node, EDA industry observers tend to worry—and perhaps with justification—about the readiness of backend tools for those new generations of fabrication technology. Photolithography equipment has seen remarkable progress in recent years, with current immersion technology staying just ahead of the curve (with a huge assist from gains in reticle-enhancement technology). But it’s becoming increasingly apparent that so-called next-generation lithography is not going to arrive in time to prop up yields at advanced process nodes such as 22 nm. Scanners with 193-nm light sources have been used since the 130-nm node; it’s becoming increasingly challenging to maintain yields with successive process shrinks.
So the semiconductor industry has turned to creative software approaches to make up the widening gap between the sizes of physical features on wafers and the wavelength of the light used to pattern them. One such approach that’s gained traction is computational lithography, a method of overcoming limitations in the manufacturing process by using computationally-intensive numerical methods to modify the shape of the masks and characteristics of the illuminating source at each layer of an IC in such a way that the result after exposure is closer to the intended shapes.
As part of IBM’s computation scaling initiative to create the industry’s first computationally-based process for production of 22-nm semiconductors, the integrated device manufacturer has entered into a pact with Mentor Graphics to jointly develop and distribute next-generation computational lithography software. Together, the companies hope to enhance the imaging capability of lithographic systems used in the manufacturing of ICs at 22 nm and beyond.
IBM and Mentor are planning to combine a number of their respective technologies and extend the work done together in developing the Cell Broadband Engine processor. According to John Sturdivant, director of RET technology support for Mentor Graphics, “Things that would have been untenable two or three years ago are now in grasp.”
Because the same process equipment that will be employed at the 32-nm node must also be used at the 22-nm node, IBM and Mentor Graphics will resort to double patterning techniques to effectively relax the pitch, which gates resolution. “We also felt there was an opportunity to eke out more process window,” says Sturdivant. One means of doing so is to focus on the delivery of the illumination light onto the mask in the so-called illumination source. Through this avenue, IBM and Mentor are envisioning a new level of optimization in the sourced plane.
In addition to optimizing the light source, mask optimization is another area of concern (see the figure). “This has been done, until now, with iterative optical proximity correction (OPC) techniques,” says Sturdivant. “Now we’ll simultaneously optimize the light impinging on the mask and the mask pattern itself. This will give us more resolution.”
Mentor’s part of this effort centers on building onto its existing Calibre RET/OPC platform; it will contribute to the integration effort with source-optimization algorithms. IBM will contribute from the process side, delivering new numerical methods and algorithms for further integration into Calibre.
Joint development work will take place at Mentor’s San Jose, IBM’s East Fishkill and IBM Research’s Yorktown locations. Silicon production at the 22-nm node is envisioned for early 2011. To that end, Mentor is targeting the summer of 2009 for beta software.