Electronic Design

IBM, Synopsys Partner On Foundry Flow

IBM and Synopsys are developing a design reference flow for IBM's 0.13-µ>m process technology that will give foundry service customers a smooth path from chip design to production. The RTL-to-GDSII flow is based on a suite of Synopsys' back-end tools, including Floorplan Compiler for design planning, Physical Compiler for unified synthesis and placement, and Astro for routing. The reference flow is being validated in silicon using a test chip that incorporates technology from several sources, including IBM, Synopsys, ARM, and Artisan Components. Availability is planned for the first quarter of 2003. For information, visit www.ibm.com/chips and www.synopsys.com.

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