IBM, Synopsys Partner On Foundry Flow

Jan. 20, 2003

IBM and Synopsys are developing a design reference flow for IBM's 0.13-µ>m process technology that will give foundry service customers a smooth path from chip design to production. The RTL-to-GDSII flow is based on a suite of Synopsys' back-end tools, including Floorplan Compiler for design planning, Physical Compiler for unified synthesis and placement, and Astro for routing. The reference flow is being validated in silicon using a test chip that incorporates technology from several sources, including IBM, Synopsys, ARM, and Artisan Components. Availability is planned for the first quarter of 2003. For information, visit www.ibm.com/chips and www.synopsys.com.

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.