EE Product News

IC Design Tools Well-Suited For Sub-Micron IC Designs

Layout, detailed verification, and automation with versatility and ease of use are combined in LAYTOOLS, a suite of programs said to be well-suited for sub-micron IC design. The suite includes LAYED, an all-angles graphics editor especially developed for IC layout design that can create and process hierarchically structured databases using a rich command set. Also included in the suite is LAYVER, a sophisticated layout verification package that offers database layer operations, design rule checking, circuit extraction, and netlist comparison all in one package. LAYPAR uses advanced algorithms to automatically locate and interconnect large numbers of cells and macro blocks. The users may optimize the results for their particular application by defining options at both the placement and routing stages.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish