It's getting harder in today's IC design flows to observe on-chip signal data. In full-chip regression simulation runs, dumping all signals for analysis is prohibitively expensive. Thus, designers must become selective. The problem intensifies in emulation, prototyping, and actual-chip observation, because access to signal data requires the insertion of logic structures into the physical hardware.
Seeking to overcome "the visibility problem," Novas Software has introduced its Siloti family (see the figure). These products, used in the near-and post-silicon stages of the design cycle, give verification engineers more visibility into the functional behavior of complex ICs.
Siloti enhances the discovery of latestage bugs by analyzing limited signal data. It also automatically derives missing data and correlates low-level design representations with RTL descriptions. Siloti is being rolled out in application-specific configurations, and two are available initially.
Silote SilVE works with emulators, prototypes, and DFD-enabled (design-for-debug) chips to optimize signal observability. It compiles the HDL design and uses formal analysis to determine which signals are essential. This information guides insertion of access points so required signal data can be obtained during-emulation or prototype operation. Siloti's abstraction correlation and dataexpansion engines then team to automatically map the low-level structures of the actual chip up to the RTL level and expand the dumped data to fill in the gaps for full visibility.
To aid in emulation efforts, Novas and EVE have announced interoperability between Siloti SilVE and EVE's ZeBu hardware-assisted verification platform.Output from Siloti's analysis is sent to the ZeBu platform, which then sets probes on the registers that Siloti deems critical. ZeBu dumps the collected signal data directly in Siloti's native signal format, and Siloti reads in the data and calculates the combinational nodes.
Siloti SimVE works with standard HDL simulators to make regression simulation more efficient. SimVE users can achieve full-chip functional debug with a single regression run.
Both Siloti SilVE and SimVE are available now. Each starts at $65,000.