The "power problem" for today's large systems-on-a-chip and ASICs is becoming intractable. Process scaling no longer is a viable means of meeting power-management needs. A design-based solution to the problem is going to be required, especially with 65-nm processes coming online.
The Power Forward Initiative is the EDA industry's effort to surmount the obstacles to lower-power IC design. Spearheaded by Cadence Design Systems, eight founding companies have joined in the effort to link design, verification, and implementation. Members also include Advanced Micro Devices, ARM, ATI Technologies, Freescale Semiconductor, Fujitsu Ltd., NEC Electronics, and Taiwan Semiconductor Mfg. Co.
The consortium's members plan to take an open and standards-based approach to building an automated design infrastructure aimed at reducing chip power consumption (see the figure). Toward that end, the group's first goal will be the creation of a unified specification format that captures essential lowpower design intent.
According to Jan Willis, senior vice president for industry alliances at Cadence, the situation can be paralleled to that of the infrastructure for logic design. "Through the years, we've standardized logicaldesign information so that it can make use of standards and an ecosystem. It's amazing how chaotic and ad hoc the industry is with regard to a design-based power infrastructure," says Willis.
"There's no standardized methodology, and constraints and design intent are fragmented. It's very difficult under these conditions to move the industry forward to automate the power-design flow," Willis continues. The launch of the consortium can be considered a "call to action," according to Willis.
The effort will begin with the Common Power Format (CPF), a broad-based specification language for stating low-power design intent across the flow. The CPF will enable all design-and technology-related power constraints to be captured in a single file that can be applied universally. It's hoped that membership feedback can be incorporated by 2007 and a standardization proposal readied by 2008.
Cadence Design Systems