Electronic Design

Integrated DFM Technology Takes Aim At 65-nm Designs

You can pick your poison when it comes to implementation flows. Chips can be taped out with flows from any of the three major vendors that offer them (Cadence, Magma, and Synopsys).

But it's increasingly clear that at 65 nm and below, an integrated flow is essential to first-silicon success. This is especially true of DFM methodologies, in which characterized process data must be kept consistent throughout the implementation flow.

To meet designers' needs in the DFM realm, Magma Design Automation has put together an integrated "characterization-to-silicon" DFM flow targeting 65-nm designs. Within the flow is the company's SiliconSmart DFM tool for model characterization, Talus DFM for design implementation, and Quartz DRC-Litho for signoff verification (see the figure).

With this flow, according to Magma, users can accurately predict, prevent, and correct DFM-related problems in their designs. Signoff-accurate DFM compliance checks within the implementation flow simplify handoff to manufacturing.

SiliconSmart DFM gives users a variability-aware characterization environment for generating models for statistical timing and leakage analysis. With the tool, designers can accurately model the subtle electrical effects stemming from process variability.

For implementation, Talus DFM addresses both random and systematic yield loss by providing foundry-accurate cell yield and interconnect yield prediction, prevention, and correction. In addition, Quartz SSTA uses statistical methods to deal with variability, enabling designers to avoid excessive design margins and reduce pessimism. Finally, on the verification side, Quartz DRCLitho lets designers perform analysis on actual silicon shapes and not on drawn images.

Contact Magma directly for pricing and delivery information on the tools in its integrated DFM flow.

Magma Design Automation

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