Electronic Design
Intelligent Testbench 101

Intelligent Testbench 101

Functional verification of large SoC/ASIC designs has always been a catch-22 situation. How does the verification engineer decide that enough simulations have been run on a functional block or full chip? When has he or she thrown enough test vectors at the design to be confident that sufficient coverage has been achieved? Theoretically, one can continue running regressions until the end of time and never find every last bug. But time-to-market pressures and market windows generally conspire to thwart such notions. So what the EDA industry has tried instead is to develop functional verification strategies that eschew test-vector quantity for quality. These strategies are known by some as “intelligent testbenches.”

Creation of a functional testbench, or the suite of test vectors that are used to validate the design’s functionality in comparison with a functional specification, is a rather inexact science as historically approached. Long gone are the days when the circuit’s designer(s) could write directed tests, or test vectors that are aimed specifically at the circuit’s intended functionality. Circuit complexity has made that approach untenable as there are generally way too many unintended functional states for the design team to even anticipate, much less write tests for.

Directed testing first gave way to constrained-random test generation, which is the mother of test-vector quantity. The use of constraint solvers allowed engineers to write constraints that reined in the randomness of the vector generation. But constrained-random testing will still leave some gap between what was designed and what was tested.

The intelligent testbench, then, is a concept that endeavors to apply a greater degree of insight to the creation of directed tests while relying far less on random test generation, constrained or not. In some of the stricter definitions of the intelligent testbench, the concept encompasses automation of the tool flow, including formal verification, and the automation of the methodology. However, not every vendor of intelligent-testbench technology necessarily complies with that caveat.

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