A just-released version of the SonicsMX SMART Interconnect from Sonics Inc. adds seamless connection and data-flow services management for intellectual property (IP) cores implemented using the ARM AMBA 3 AXI interconnect. Previous versions support OCP 1, OCP 2 (open-core protocol 1 and 2), and the ARM AMBA 2 AHB protocols. By adding support for AMBA 3 AXI interconnect to the existing OCP and AMBA AHB protocols, the new version promises to greatly simplify the system-on-a-chip (SoC) developer’s overall task.
The SonicsMX SMART Interconnect offers straightforward management of the heterogeneous mix of processing units. It delivers high memory bandwidth with guaranteed quality of service, highly flexible pipelining options, embedded firewalls for content protection, and error and power management. SonicsMX also provides socket support for mixing and matching data widths, clock frequencies, and protocols, including seamless support for advanced AMBA 3 AXI interconnect-based cores such as CPUs.
With the unification of the interfaces into SonicsMX, designers can model all the SoC data flows during the architecture design phase of the SoC development, which can dramatically reduce design times. Using the SonicsMX interconnect, SoC designers can rapidly integrate high-performance ARM CPUs, including the ARM1176JZ-S processor and the ARM11 MPCore processor. The addition of native AMBA 3 AXI interconnect support enables designers to efficiently implement processor to memory data flows and build systems with multiple interfaces in a well-structured manner.
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