Electronic Design

I/O Fabric Generator Spins Complex SoC Designs

The Spinner I/O fabric generation tool for automated, bug-free I/O fabric synthesis of complex SoCs is said to automatically generate and validate the RTL for the complete I/O layer of an IC from a single-source specification. Using the tool’s so-called “Perfect By Construction” methodology, SoC designers can eliminate I/O bugs and greatly simplify the integration effort—with up to three-times fewer resources, five-times schedule reductions, and radically improved quality through sign-off level collaboration on incremental changes, accordion to Duolog Technologies.

The Spinner is intended to address the spiraling complexity of SoC I/O integration, which finds design teams under enormous pressure to deliver bug-free designs the first time around. I/O design bugs can delay system validation, and silicon bugs can kill the chip. At 45 nm, one respin typically costs more than $4 million, and a three-month respin delay can result in loss in revenue.

Duolog’s Spinner enables a fully automated, bug-free 1-Click Release with standardized tool interfaces, extensive coherency checking and a powerful generator framework that delivers bug-free code and specifications.

Spinner’s advanced I/O fabric generation features include:

  • IP-XACT compliant interfaces for core, chip, die, and package as well as I/O layer primitives, such as I/O, DFT and BSR cells;
  • Complete SoC I/O layer specification IDE for pin muxing, I/O-cell control, BSR and package definition;
  • Coherency checking to perform an exhaustive range of checks on the I/O specification;
  • Auto-generation of I/O fabric RTL, documentation, validation and software views and IP-XACT interfaces.

Eclipse-based Spinner runs on Windows, Linux, or Solaris and is highly interoperable with existing design flows through standards-based interfaces. The tool is available now with multiple licensing options; contact Duolog directly for pricing information.

Duolog Technologies

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