At 130 nm and below, it's essential that designers get a leg up on yield. IP providers have begun to understand that they're in a good position to help their customers do so by building process awareness into their products. To that end, Virage Logic has rolled out its Silicon Aware IP initiative to maximize yield and enhance time-to-volume.
Silicon Aware IP is physical intellectual property (IP) such as memories, logic, and I/O that incorporates embedded infrastructure IP for test, diagnostics, repair, and yield enhancements. Conventional approaches use independently optimized infrastructure IP and physical IP, which can mitigate against the two working together in an optimal manner.
Virage's approach builds on its Self-Test And Repair (STAR) memory system, which recently saw its third-generation launch. The latest STAR incarnation adds improved testability and repairability to the memories. In the Silicon Aware IP initiative, Virage has extended the STAR concept to its logic and I/O families.
A recently announced partnership with PDF Solutions will enable Virage to add infrastructure IP to its Area, Speed And Power (ASAP) logic libraries. By working with its foundry partners, Virage is implementing the foundries' yield-improvement guidelines in its standard cells.
PDF extensions to the libraries will result in variants of cells that target fab processes at different levels of maturity. When a process is in its early stages, designers will be able to replace the base version of a cell with a variant that compensates for the process' shortcomings until it reaches maturity, dramatically enhancing yields.
Virage also plans to package memory, logic, and I/O cells in application-specific groupings under its IPrima Foundation platform approach. The company also has expanded its distribution model and adopted a "foundry pays" approach, making IPrima Foundation IP free to customers. DongbuAnam, SilTerra, SMIC and Tower Semiconductor have signed on under the new model so far.
Virage Logic
www.viragelogic.com
