Five intellectual property (IP) cores have been developed for use in communications, networking and telecomm praoducts. They include an 8b/10b encoder/decoder, a configurable cyclic redundancy code (CRC), a SDRAM controller, a PCI bus arbiter, and UART. When implemented in the company's SX-A or eX devices, the cores are said to offer designers the benefits of faster time-to-market, reduced design cost and performance advantages. The cores are provided as source RTL code, making them both portable and flexible. They are written in HDL code and supplied in Verilog or VHDL, and each core includes documentation and testbenches. The encoder/decoder is used for the physical coding sub-layer employed in Gigabit Ethernet and fibre channel and supports data rates in excess of 125 MHz. The encoder/decoder also provides disparity and illegal code error checking. The CRC generator validates data frames and ensures that data corruption during transmission is detected. It also supports operating speeds of up to 270 MHz, as well as various communications standards, including ATM, CANbus and X25. Licensing costs for the cores start at $495.