Electronic Design

IP Helps Characterize Intra-Die Process Variability

DFM techniques can go only so far in ironing out intra-die process variability. That's because DFM techniques to date haven't fully addressed parametric yield issues.

Stratosphere Solutions, a Sunnyvalebased startup, thinks it has an answer to the acceleration of process yield ramps. In a nutshell, the key to comprehending and reducing design-related yield loss lies in statistical parametric characterization based on actual measured silicon data.

Intra-die process variability can result in undesirable and maddeningly unpredictable shifts in electrical behavior that adversely affect a circuit's functionality. It has become prohibitively expensive to characterize these parametric failure mechanisms using traditional means.

Stratosphere's StratoPro approaches the management of yield through a combination of a silicon-IP platform and tools that characterize intra-die device variability,-which enables accurate parametric yield analysis (see the figure).

The platform brings together three elements. The first is comprehensive characterization of process variability using measurements derived from silicon. The second is analysis, quantification, and modeling of yield based on that variability. And, the third is optimization of design performance using yield models.

Manufacturers can incorporate Strato-Pro on their test vehicles, fabricate the wafers, and then test using the StratoPro tool suite. The measured output is incorporated into the manufacturer's yieldmanagement system.

StratoPro is available in a full-reticle version for early process development and yield ramp, as well as a scribe-line version that's most useful for production monitoring. A yield-modeling environment is under development that will enable fabs to feed comprehensive yield models back to designers without divulging process secrets.

StratoPro is licensed per process node and fab site. List price starts at $350,000 for a perpetual license.

Stratosphere Solutions

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