The Interoperable PCell Libraries (IPL) Initiative has issued an open invitation to semiconductor companies, foundries, integrated device manufacturers (IDMs), and EDA companies to join its three newest technical working groups. The groups seek participants to contribute to standards on Properties and Parameters, PCells, and Constraints. The IPL Initiative, first formed in April of this year to address PCell interoperability issues, has expanded its charters to address broader interoperability issues with foundry process design kits (PDK) and design flows.
Standardization of PDKs and design flows benefit analog and custom IC designers by removing bottlenecks in multiple-vendor flows (see “Analog/Full-Custom Flows Move Toward Interoperability,” http://electronicdesign.com/Articles/Index.cfm?ArticleID=16028). Currently, each foundry is creating specialized PDKs for different EDA vendors and tools. Without standardization, analog design houses are limited by incompatible non-extended kits from foundries and limited support for newer, more advanced tools. The result is increased cost, extended schedules, redundant efforts and impeded innovation.
The companies involved in the technical working groups are Applied Wave Research (AWR), Ciranova, JEDAT, Magma, Silicon Canvas, Silicon Navigator and Synopsys. All companies involved are members of the IPL initiative. Other companies have been invited to participate. The IPL initiative is now actively looking for knowledgeable individuals to participate in the working groups.
Any party interested in participating in the IPL working groups should contact Jingwen Yuan, Strategic Alliance Manager of Synopsys Inc. at: [email protected]