Electronic Design

It's Time To Lift The Burden From Logic Designers

These are not easy times for logic designers. As geometries shrink and chips grow ever larger and more complex, more and more design decisions are being pushed up to the RTL stage. When these decisions are made incorrectly, the result is long iterative loops between back-end processes and RTL, leading to unpredictable tape-out dates.

For example, it used to be the case that power could be tweaked in the layout stage by selecting different buffers. Today, with 80% of the power consumption determined by the architecture and the RTL implementation, there’s not enough flexibility in the later stages of the project to fix things if the power budget is exceeded. Using multiple voltages or allowing parts of the chip to be powered down is a good solution, but deciding this at layout has painful ripple effects back to the logic designers.

The same situation exists for testability problems, timing failures due to unanticipated layout issues, and corner-case bugs found during chip-level verification. In each case, the loop back to the designer means lots of work to understand the problem, devise a solution, and change the RTL. The situation is even worse if the designer tries to respond to contradictory feedback loops from multiple tools. It is little wonder that designers sometimes feel as if all the weight of the project is on their shoulders.

The solution is to integrate these four dimensions of design—power, test, physical, and verification—into the early stages of the project to minimize the chances of unpleasant surprises later. This "design-with" approach sometimes looks as if it requires even more work from the designers, but in fact it trades off a bit more effort up front in exchange for a huge reduction in late-stage RTL changes.

Design with Power

Integrating power requirements into the entire design flow benefits designers in two ways. First, they make the critical power-management decisions during RTL coding, eliminating iterative loops back from layout tools. In addition, they no longer have to manually insert isolation cells between power-down domains or level shifters between voltage islands. Implementation tools can do this automatically given a power specification.

Logic designers can now capture their intent in a power-specification file that is used by every design, verification, and implementation tool in the flow. Simulation and formal analysis can check the correctness of power-up and power-down sequences, synthesis tools can include appropriate cells such as level shifters, and layout tools can create a power-aware chip that matches the original specification.

Design with Test

Similar automation has largely eliminated any burden at all for designers in the test domain. Testability insertion tools can add scan, JTAG, and BIST logic to the design with minimal intervention or specification. The logic designers simply indicate which test techniques are to be used, and perhaps provide a few dedicated or multiplexed pins. Some test tools can even read the power specification file to ensure that the chip does not melt while it is on the tester.

Design with Physical

In today’s deep-submicron chips, routing wires account for far more of the timing delay than the gates themselves. Thus, a tight correlation between the static timing analysis during synthesis and the actual chip layout is essential to avoid rework loops from place and route back to RTL. Traditional wire load models are not sufficient; automatic physical layout estimation must model physical effects to a high degree of accuracy during the synthesis process.

Design with Verification

The earlier a bug is found, the less it costs to diagnose and fix it. Therefore, designers must become more involved in the verification process. Design with verification hinges on two techniques that have been proven highly effective. The first is comprehensive specification of assertions to document design intent, followed by early and proactive use of formal analysis to prove assertions and find design bugs without requiring a testbench.

When block-level simulation is desired, the technique of module-based testbench development comes into play. This empowers logic designers to develop constrained-random, coverage-driven testbenches without having to become experts in class-based, object-oriented programming. Both this approach and formal analysis enable designers to find bugs early in the project rather than spend days tracking down the source of each deeply buried bug found in chip-level simulation, acceleration, or emulation.

Justifiably, logic designers at times feel that they are being asked to shoulder more and more project responsibility. This is inevitable, given that so many critical decisions must be made at the RTL stage or earlier. However, it is not inevitable that this responsibility implies more work. Design with power, design with test, design with physical, and design with verification are powerful and practical techniques that deliver great benefit for logic designers and for the project as a whole.

Thomas L. Anderson is product marketing director for Cadence Design Systems Inc., San Jose, Calif.

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