Some people believe that the wireless Internet may very well be the "killer application" for 3G. After all, it is a valuable medium for the transmission of many types of communication, including data, voice, streaming content, e-commerce, and news. In fact, the wireless Internet's list of potential uses continues to grow every day. For their part, Internet users contribute to these positive forecasts. They want access to such communication information everywhere and without restriction. Wireless technology claims to be able to fulfill this promise.
One of the wireless solutions gaining popularity—especially in South Korea and Japan—is 1xEV-DO. This technology is an extension of cdma2000. It offers data transmission that is up to 10 times the rate of the IS-95 system and up to three times the rate of cdma2000 from base station to subscribers. 1xEV-DO is defined in the 3GPP2 specification denoted C.S0024. Its U.S. version, which hails from the Telecommunications Industry Association (TIA), is referred to as IS-856. The 1xEV name was originally coined during the standards process. At this time, the recommended capabilities of cdma2000 were amplified with a 1xEV mode that was optimized for high-capacity/high-speed data and Internet access (1x EV-DO or "1x evolution, data only"). They also were highlighted by an integrated mode that was optimized for voice and data (1x EV-DV, where DV means "data and voice"). This article attempts to provide a brief description of the key features of 1xEV-DO. It also provides an example of how a system engineer could successfully conduct verification on a design based on this technology.
Structure And Operation
1xEV-DO relies on the fact that a given user's Internet data transmission is bursty. This means that the link is idle most of the time. It assumes high throughput only during short "bursts." By consolidating the statistics of data-transmission latency for multiple users, it is possible to pack a number of users on a few physical channels in the forward link. These users would be efficiently scheduled and assigned priorities. The sharing of a single carrier then becomes possible by utilizing a Time Division Multiplexing (TDM) technology in a cdma system's forward link. As a result, data is directed to only one Mobile Station (MS) at a time during data transmission. The full power of the base station can therefore allow the highest possible data rate to that one user.
To reduce the final modulation bandwidth, 1xEV-DO uses the same final spread rate (1.2288 Mcps) and the same digital filter as IS-2000 SR1. 1xEV-DO is spectrally compatible with IS-2000 SR1. To cut installation costs, similar RF transmitter systems like amplifiers, combiners, and antennas can therefore be used on both 1xEV-DO and IS-2000 SR1. 1xEV-DO cannot be overlaid with IS-2000 channels, however. Each 1xEV-DO channel requires a paired 1.25-MHz clear channel.
Instead of having traditional base stations and mobile stations dedicated to voice transmission, 1xEV-DO has Access Network Points and Access Ter-minals. Four different channels are used in the forward link: the Traffic channel, the Preamble channel, the MAC channel, and the Pilot channel. Figure 1 depicts the 1xEV-DO forward-link baseband model.
By definition, the forward-traffic channel is a variable-rate channel. In other words, the data packets are turbo-coded, scrambled, repeated, punctured, demuxed, and then summed in Walsh space. At this point, data is fed into a modulator. That modulator utilizes one of the QPSK, 8PSK, or 16QAM modulation formats. The resulting sequences of symbols are demultiplexed to form 16 pairs of parallel I and Q streams.
Designs should be verified against the original 3GPP2 specifications. In traditional processes, engineers verify prototype components, subsystems, or complete systems using manual test benches. If the efficiency of these processes can be improved, a reduction can take place in design-cycle time. This verification is accomplished through the use of simulation software. Such software has become the engineer's primary choice for verifying a design against system-performance requirements. By reducing physical prototype iterations, tools that integrate simulation and (early) prototype verification can significantly improve efficiency.
An environment that facilitates RF design and verification for a given standard would need to include integrated baseband, signal-processing, and digital effects. These effects would complement the RF sources, measurements, components, and subsystems. Such an environment is ideally an RF/mixed-signal environment with the following:
- RF and baseband behavioral models that are built around requirements
- Preconfigured simulation setups that facilitate fast verification
- Flexible and seamless links from virtual simulation to instruments and vice versa
- Intellectual-property (IP) design and guides for re-use and exploration
Let's review the requirements of design and verification for 1xEV-DO. The set of models that is needed should be configured to provide the most flexibility of selection per standard. At the same time, it should require the least user knowledge of specification details. For example, the source for generating the 1xEV-DO forward-link signal should automatically map the rate to the modulation scheme (QPSK, 8PSK, and 16QAM) and/or slot format (FIG. 2).
The unique structure of the 1xEV-DO signal also demands special measurements. Granted, 1xEV-DO does use traditional modulations like QPSK. Because the data-channel modulation occurs before Walsh spreading, however, it is not possible to analyze the data with traditional QPSK, 8PSK, or 16QAM measurements. Instead, a special demodulation measurement is needed that is specific to the 1xEV-DO standard. Similarly, the frame structure includes both active slots (where data is sent on the forward link) and idle slots (where no data is sent) with a varying duty cycle. As a result, both power measurement and ACPR require unique definitions. Figure 3 shows the 1xEV-DO frame-signal simulation with varying duty cycles.
As an example, say that a designer's goal is to verify the performance of an RF amplifier as a driver for a 1xEV-DO transmitter. He or she can utilize the environment for 1xEV-DO design and verification that is now available in the Advanced Design System (ADS) software tool. The user must simply follow several steps that combine the power of behavioral and circuit-level simulation with on-bench verification. In the latter case, verification involves coupling both prototype hardware and instruments with links to simulation software (FIG. 4).
This example uses one of the existing setups for 1xEV-DO: Power Measurement. It replaces the Device Under Test (DUT) with a more detailed RF-transmitter front end. This transmitter includes two IF stages and one RF stage. The parameters of the design and schematic used are shown in Figure 5. At this stage, the user may opt to purchase an existing part or re-use a circuit design that has already been proven effective.
For the pre-amplifier model, begin with a behavioral model of an off-the-shelf part, such as Agilent's MGA 72543. This amplifier can be biased to operate as a low-noise amplifier (LNA) or driver amplifier. The TOI increases as the bias current is raised, allowing the MGA 72543 to be used as a driver amplifier when operating at a higher bias current. This device also can be bypassed. It saves current when transmitting at a lower power.
Preconfigured setups exist for checking other system requirements, such as power versus time, Rho, and Code Domain Power (CDP). By utilizing them, the user can test the performance of the behavioral amplifier. A preconfigured setup would indicate whether the design has "Passed" or "Failed." Figure 6 shows the power-versus-time test setup with masks, as it is defined in the 1xEV-DO specification.
Once this driver amplifier's overall specifications are identified, the transistor-level circuit design will begin. It will be based on the requirements that were obtained at the system level. They include gain, output TOI, and 1-dB compression.
Once the transistor-level design becomes available, its performance is verified in simulation. The circuit is placed in the preconfigured system-level setup. Co-simulation of the circuit and system-level designs is then performed to make sure that the circuit satisfies the system-level requirements of the transmitter (i.e., acceptable ACPR and Rho per the 1xEV-DO specification). The use of a low-level transistor model in a system-level simulation may turn out to be time consuming and inefficient, however. This is certainly the case if system-level design verification requires the optimization of one or more parameters against several system-performance goals. In such cases, the simulation time may become long, impeding the objective of reducing design-verification time.
The extraction of a model from transistor-level design or measurements closely duplicates the physics of the design. In simulation, this process involves generating data sets. These data sets closely replicate model behavior.
In the example, a p2d model of the pre-amplifier was generated. Seven harmonics were used to extract an AM-to-AM representation using Harmonic Balanced simulation. Figure 7 shows the comparison of the behavioral, circuit, and verification models for the pre-amplifier.
Simulation And The Real World
At this stage, the verification model provides the best fit. It passes all of the transmitter requirements when stimulated with the 1xEV-DO signal. The next step involves building prototype hardware. Fortunately, the hardware prototype for this example is already available. It can be excited with the "real-world" version of the "virtual" stimulus, which was utilized in the simulation environment described previously. It can be achieved through the seamless instrument link between Agilent EEsof's Advanced Design System and the ESG signal generator utilized on the bench.
To obtain this prototype, download the I and Q signal from the simulation world into the instrument as arbitrary waveforms. Note that this signal could be different from the native ESG signal. It may include distortions from the impairments that were modeled into it during simulation.
Next, excite the prototype amplifier with the ESG signal initiated in software. At this stage, the user has the option of adjusting the test signal at any desired RF frequency and power level. To make the proper measurements, the amplifier's output can be directly fed into a vector signal analyzer or a performance spectrum analyzer (FIG. 8). These measurements can then be compared with the simulated results of the 1xEV-DO transmitter. Use both behavioral and extracted models of the driver amplifier's circuit-level representations. The comparisons can then be used to debug or optimize the design. The result is a high level of confidence in the model and the prototype. Most importantly, the designer also gains faith in the overall system performance.