Basic rule-checking capabilities for all SystemVerilog 3.0 design constructs are now available in the nLint tool. Continuing to drive support for the Accellera SystemVerilog standard, nLint enables early detection of design problems in IC development methodologies.
The nLint tool, developed by Novas Software, works with the company's Debussy and Verdi debug systems. It's an easy to use HDL design-rule checker that analyzes SystemVerilog, Verilog, and VHDL source code for syntax and semantic errors. Support for System-Verilog 3.0 design constructs includes a comprehensive set of standard and parametrized rules. These include checks to ensure proper SystemVerilog modeling with specialized procedure statement blocks. Tool users can implement custom rules as well.
Also, nLint operates on the same underlying knowledge database used by the Debussy and Verdi debuggers for access to full connectivity information. As a result, designers can check all types of data and visualize design-rule violations in their debug environments.
Now available in limited production, the general product release of nLint for SystemVerilog 3.0 is scheduled for the fourth quarter of 2004. Purchased as an option to the Debussy and Verdi debug suites, nLint starts at $5000 for a one-year subscription license.
Novas Software Inc.