Electronic Design

Lithography Awareness Reaches Front-End Design Tools

For IC design at the 90- and 65-nm process nodes to be truly successful, the design process needs more predictability built into it in terms of yield. The problem, to a large extent, is that there has been little in the way of awareness of lithography issues in the design flow. Today’s flow for lithography mask preparation centers on optical proximity correction (OPC) and lithography rule checking that are performed after layout, which is obviously a post-design scenario. But waiting that long in the process can mean losing the battle for higher yields altogether. By then, the ability to make changes without the pain of having to cycle through design closure again is in serious jeopardy.

With the release of the Virtuoso RET Suite, Cadence Design Systems is hoping to bring awareness of the lithography process as far forward into the design cycle as possible. The Virtuoso RET Suite allows designers to analyze and optimize designs for both performance and yield by examining precisely how target layout structures will appear in silicon. This is achieved by precisely modeling the distortions that are inherent in sub-wavelength lithography.

“Bringing lithography awareness into the design process is difficult to do as a bolt-on or external tool,” says Mark Miller, VP of marketing and business development. “To be done effectively, it has to be integrated into the existing flow.” To that end, the Virtuoso RET Suite incorporates interactive model-based simulation of layout designs; batch and interactive lithography rule checking; lithography-yield analysis and optimization; and trial-based optical-proximity-correction (OPC) capabilities using critical lithographic parameters, including illumination mode, exposure, and focus.

There are four primary ways in which the Virtuoso RET Suite builds lithography awareness into the Cadence Virtuoso layout environment, says Miller. “First, it’s in putting the design together in the Virtuoso (for custom digital and/or analog/mixed-signal design) or Encounter (for cell-based digital design) environments. Place-and-route works primarily on the interconnects; we’re looking to address the harder part of the problem.”

The suite figures in traditional OPC processes and lithography rule checking. It also is applicable to lithography process development, where engineers look one or two process nodes down the road in attempts to come up with a lithography “recipe,” or sequence of events and style of optical-proximity correction that can produce good yields for those future process nodes. This is how the design rules are developed that would be used in the Virtuoso and/or Encounter design environments.

There are four key components to the suite. The Virtuoso RET Imager simulates the impact of lithography processes on layout to create images of the resulting silicon. This tool can use default process conditions for its simulation, or it can use a specific Process Model File (PMF). The latter is a new proposal for a standard, secure courier of detailed and confidential manufacturing information that’s seamlessly integrated to the Virtuoso environment.

The second element, the Virtuoso RET Verifier, tests the shapes produced by the Imager against lithography rules to flag violations that may affect yield. The use model for this tool is similar to design-rule checking.

Third is the Virtuoso RET Designer, which interactively inserts trial RET features into the layout to evaluate their effectiveness in preserving intended feature shapes despite lithography distortions. “This tool enables users to look at their library cell by cell,” says Miller, “and to come out of the process with a DRC- and lithography-clean library.” With Designer, users can find areas of deficiency in their libraries, move back into the source data to make changes, and then rerun Verifier to validate those changes. Designer operates incrementally from one polygon to one IP block at a time. It also can check whole layers and can then be rerun for adjacency effects when cells are combined.

Finally, the Virtuoso RET Analyzer quantitatively analyzes the results from Imager to compare and tune alternative RET approaches. In doing so, it evaluates the design’s sensitivity to lithography-process variations. The design is examined over a range of process conditions with respect to parameters including dose and focus to check sensitivity across the process window.

Essentially, there are two primary use modes for the Virtuoso RET Suite. One is for development of lithography-process recipes for OPC; the other is for quick checks on the layout side for expected sensitivities to process variation. Elpida Memory is already using the Virtuoso RET Suite for lithography recipe development for the 45- and 32-nm process nodes.

Contact Cadence directly for pricing and delivery information.

Cadence Design Systems
www.cadence.com

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