Claimed as the most comprehensive high-density, in-system programmable design solution, ispDS+ version 5.1 HDL synthesis-optimized logic fitter has been upgraded to include enhanced ispLSI design features, including ispTA static timing analyzer, new device support, and greater ease of use. Leading CAE vendor support for Viewlogic, Synario and Synplicity Toolsets is also a welcome addition. The built-in static timing analyzer has been upgraded to include path enumeration options, the generation of a variety of important timing reports, and easier access to all reports. The system's Explore Tool has also been enhanced to provide the user with more control over design implementation and to easily identify the most efficient logic compiler settings for a design. New device support includes firm's ispLSI 3320 and isp LSI 3448 PLDs. Also included is support for BGA packages, now offered with all ispLSI 3000 family devices having more than 200 leads. The package is supported on both PC and workstation platforms.