Electronic Design

Low-Power Design Flow Exploits UPF Support

Low-power design is a systemic discipline, so it naturally follows that a design flow intended to address low-power design should also approach the task from a holistic point of view. This has been Synopsys’ goal with its new Eclypse platform for IC designers.

For just about half of Synopsys’ major customers, power consumption is a major design constraint. Most of them are well aware of the techniques prevalent among design teams today for managing power, but they’re too often overwhelmed by the task and ill-prepared to tackle it.

A key element of the Eclypse flow is its native support for the Unified Power Format (UPF), one of two competing formats in the industry today for defining power intent throughout the design flow; the other being the Common Power Format or CPF (for more on power-intent formats, click here.) All of the tools in the Eclypse flow, from the VCS simulator through Prime Time for static timing analysis, support UPF, which is now in the process of being standardized as IEEE-P1801. Previously, supporters of the competing CPF standard cited lack of tool support as a major downside of UPF. Synopsys’ support, coupled with support from Magma Design Automation and Mentor Graphics in their own toolsets, levels the playing field somewhat. CPF already enjoys tool support from Cadence Design Systems, its key champion.

The flow also offers automated clock-tree synthesis that’s enhanced so that clock skew and power consumption are both optimized. Synopsys’ Power Compiler performs clock-tree rebalancing with both of these constraints in mind, adding or subtracting levels of logic from the clock tree to achieve the best combinations of skew and power draw.

A very important element of developing a power architecture is the analysis of power-switch placement. Having too few switches can cause IR-drop issues; too many chews up area needlessly and wastes routing resources. The Eclypse flow automates that analysis, determining the optimal configuration for power-switch placement. Users can feed the tool a series of configurations, which the tool analyzes and reports on in the form of a table. For each configuration, the IR drop and area penalty is shown, allowing the designer to choose the tradeoff that best suits the design.

The VCS simulator has been enhanced with technology Synopsys acquired along with ArchPro Design Automation in 2007. ArchPro’s multi-voltage simulation engine attaches to VCS and endows functional simulation with the ability to understand the concept of disparate voltage domains. VCS is now able to automatically insert and make use of power assertions that simplify the pinpointing of power-related bugs.

For pricing and delivery information, contact Synopsys directly.


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