Power management is fast becoming one of the most critical design constraints in the world of IC designers. New 90-nm processes deliver greater silicon performance and integration, but battery technology hasn't kept up. To compensate, new design techniques are being developed to address the need for low-power silicon.
A collaboration between members of the Silicon Design Chain (Applied Materials, ARM, Cadence, and TSMC) has resulted in a demonstration of the ARM1136JF-S core module as part of an effective power-management system. The ARM1136 was chosen because of its wide application in wireless systems.
The design flow used TSMC's 90-nm G process, Artisan physical IP, including SAGE-X memories and standard cells, and a production Cadence Encounter design platform. In the flow, power was attacked on two fronts: leakage and dynamic power.
Use of ARM/Artisan physical IP was the main weapon against leakage. The team used libraries that contained a matched set of logic cells, each having different threshold voltages (VT) and the same physical footprint. The cells with the higher threshold voltages leak less than their lower-VT counterparts. The Encounter synthesis tool devised a netlist that met the desired 350-MHz performance goal with the lowest possible leakage current.
On the dynamic-power side, voltage scaling was applied to segments of the design that were deemed noncritical for performance. Timing-critical segments were kept at a 1-V supply while less timing-critical blocks were scaled back to 0.8 V, saving 36% of dynamic power for that portion of the design. To achieve this voltage reduction, 3400 level shifters were automatically inserted.
Further power reduction was accomplished through clock gating. The Cadence tools were used to automate clock gating. Additionally, some minor adjustments were made to the Cadence Encounter flow to achieve the group's goals. Those adjustments will be incorporated into the 4.2 release of the Encounter platform, which should be available now.
Silicon Design Chain Initiative