Electronic Design

Low-Power Reference Flow Targets UMC's Advanced 65-nm Process

Magma Design Automation’s reference flow for UMC's advanced 65-nm process enables designers to address low-power nanometer design considerations during implementation and within a single environment. UMC’s validation of the reference flow included QoR testing on real-world designs.

The Magma-UMC RTL-to-GDSII low-power reference flow includes required scripts and documentation to enable Magma users to ramp up to UMC's 65-nm low-power process technology. The reference flow is capable of creating multiple power domains for reduction of leakage current as well as of overall power consumption, all while meeting timing requirements.

The reference flow also provides MTCMOS power switch insertion and placement for implementing a switched domain; automatic checking and insertion of level shifters and isolation cells to the right locations in a domain; retention of flip-flops and latches in the domain which can be powered down; and always-on buffer insertion for connecting to a secondary power source. In addition, Magma's placement engines complete all the standard-cell placement in the design using features such as comprehensive congestion analysis and timing-driven placement.

Magma's clock tree synthesis constructs a minimum-skew clock tree. With the GUI clock-tree browser, users can monitor the clock tree implementation during the flow and can select the correct clock tree structures for their design. After clock tree synthesis is completed, Magma's routing engines complete the routing, including signal and power routing, based on the user's specified routing rules.

A reference-flow kit is available from Magma. Included with the kit is a summary document describing the flow, run scripts, a tutorial design, test case results, and more.

Magma Design Automation www.magma-da.com/UMCMagmaReferenceFlow.html

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