Check RTL Up Front
HDL analysis tools perform design-style checks and can be configured to automatically check your RTL for acceleration/emulation compliance. In addition to simple checks, such as verifying that your design is synthesizable, these tools can check and warn you up front that your testbench is checking for the unknown state "x" from the design. Although this is a very common practice in most simulation environments, it can wreak havoc when transitioning to hardware-assisted simulation acceleration. By enforcing such design rules up front, before simulation even starts, HDL analysis tools make the transition to acceleration-and ultimately emulation-far easier.
Have A Plan
Verification IP is becoming an increasingly critical part of your verification process. When planning your verification process, talk with your EDA vendor to make sure you have all the verification components needed for simulation, acceleration, and emulation. These include soft and hard bus interfaces models (i.e., Cadence's SpeedBridge products), soft or hard processor IP, software debuggers, and memory models.
The more of your design and testbench you can synthesize, the better. If you can synthesize the whole design and the testbench, you will get the best performance while using hardware-assisted verification tools. A design with a synthesizable testbench will run 100 to 10,000 times faster in hardware-based environments compared to a design with a behavioral testbench.