As the industry continues to press forward with 65-nm design starts and early production volumes, most of the buzz surrounding DFM has focused on the critical chip layers that form the transistor devices. These layers have the smallest dimensions and, as a result, are the hardest to print as we move well below the wavelength of light used to process wafers (in this case, 65-nm dimensions versus a 193-nm wavelength).
The debate rages on about DFM: Could, or even should, the industry try to teach designers about all of the vagaries of the manufacturing process? Over the last couple of years, there's been a significant shift toward the use of restricted design rules (RDRs) to compensate for the manufacturability issues at the smaller geometries.
This seems to be the path of least resistance to follow, since it means that only a small subset of IP and custom designers will need to comprehend the real complexities of the manufacturing process. If the IP providers can abide by the RDRs, it should ensure good manufacturability. Once the IP blocks (standard cells and larger macros) are built and verified to these RDRs, designers ought to be able to reuse them in much the same way as they have done for the last two decades.
But before we claim victory over the DFM crisis, there remains a wide chasm yet to be crossed—the routing layers of the design. At 65 nm, the dimensions of the routing layers are larger and easier to manufacture. Yet at 45 nm and below, routing-layer dimensions now resemble those of the 65-nm transistor devices.
Employing RDRs at the routing levels is a much more complex problem, because these levels are, by definition, different for every unique chip. Very little "reusability" exists in the routing levels as compared to the reuse of the standard-cell or IP-block layouts. A design's routing topology (including key aspects such as holding down congestion and meeting timing) greatly depends on placement of the standard cells and IP blocks, the number of layers available, power-routing schemes, blockages, and other factors.
In short, variability remains at the routing level. Further, we remain stuck with the question of how to fit DFM into the designer's flow. Using RDRs in routing is a less palatable solution, because it would require that many more designers be trained on manufacturability. In addition, there would be a prohibitive cost in terms of chip performance and die size.
Rather than handling DFM at the metal levels, a preferable approach is to use manufacturing-aware routing technology (see the figure). Such a router would automatically consider manufacturability during the routing process when there's global freedom to plan the space to be used. The router would be tuned once for a given foundry process by a CAD group to "design out" known process limiters. Once it's tuned, the router can then achieve timing closure while obtaining optimal manufacturability for a given design.
As we progress into deeper nanometer technologies below 65 nm, it becomes imperative that we link the design platform to the process engineering platform. This will allow for a seamless handoff between design and manufacturing.
Today, much of the design intent is stripped away before the design is sent to the fab. Along the way, the design is treated for both mask and wafer manufacturing. Unfortunately, those treatments are applied without knowledge of design intent.
At 65 nm, this approach has caused severe data-size and cycle-time problems in the mask shops. They'll only worsen as we move to smaller geometries. A software platform that enables IC designers, IP suppliers, mask data-prep engineers, litho engineers, and product engineers to collaborate and share data will eventually be required to manufacture chips in this era.