At the heart of this new multi-chip module (MCM) is a 64-bit dual-issue, superscalar MIPS microprocessor that can issue one integer and one floating point instruction per cycle. The ACT-5271SC MCM packs 2 MB of embedded secondary cache, with the 64-bit multiplexed system address/data bus said to offer optimum price vs. performance with high-performance write protocols to maximize uncached write bandwidth. And to gain increased performance in slower legacy hardware, an innovative FPGA-based FIFO structure allows the internal secondary cache bus to be operated at 2 to 3 times the external system bus rate. The CPU pipeline can run at 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, or 9 times the secondary cache bus rate to reportedly create a flexible performance optimization environment. The device is housed in a 280-lead ceramic flat pack and is expected to find use in military and hi-rel systems.