Electronic Design

Methodology Expedites Route To SoC Testbenches

By encapsulating verification best practices and combining them with large productivity gains, Verisity's System Verification Methodology (sVM) can help overcome a lack of verification expertise.

The methodology builds on Verisity's e Reuse Methodology (eRM) by codifying and enforcing rules for reusing verification IP. It adds critical technology to the company's flagship Specman Elite testbench automation tool, which simplifies the technology's adoption while increasing the intelligence of verification cycles. The result is productivity gains of up to 10× in the composition of SoC-verification (system-on-a-chip) and system-level-verification environments.

There are two key elements to the productivity boost. The first is the elevation of the verification environments' abstraction level by enabling Specman to examine sequences, or groups, of transactions. This hierarchical processing of transactions permits efficient descriptions of system-level scenarios.

The other element is the combination of the ability to process transactions hierarchically with a technology Verisity terms multichannel generation. Typical SoCs contain multiple I/Os and on-chip buses linking many IP blocks. These devices must be exercised simultaneously from all possible interfaces to control and receive data. This requires embedding of generators, checkers, and monitors for each channel, as well as multichannel constraint solving, synchronization, and coordination. Otherwise, there's no way to introduce all possible system-activity scenarios.

Included within the sVM is support for register modeling and automated device-configuration generation through a new register package. The register package offers a way to model all device registers easily. It automatically generates configuration sequences and automates much of the checking and coverage of register access and the device state.

A new product called eAnalyzer supports the sVM's best practices element. This intuitive static analyzer and methodology compliance system checks for compliance with the eRM.

To support the methodology's analysis capabilities, the Visualization Toolkit (VT) was upgraded as well. The VT provides visualization and debugging of multichannel sequence generation, which simplifies understanding and debug of chip-level environments.

An updated library package that includes sVM supporting technology will be available with the full release of Specman Elite v4.3 this month. The eAnalyzer costs $22,000 for an annual license.

Verisity Design Inc.

See associated figure.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.