Electronic Design

Model-Based Flow Brings Variation Awareness To 45 nm

Designers of SoCs or ASICs for advanced process nodes have already learned that systematic-variation issues can wreak havoc in the back end. Variations in lithography, the manufacturing process itself, and chip-finishing steps such as chemical-mechanical polishing (CMP) can result in silicon that doesn’t work as well as expected, or even at all. Guardbanding is one way to sidestep these issues, but it forces designers to compromise on performance, power, and/or area.

By adding five new technologies to its Encounter digital flow, Cadence claims to have created highly accurate modeling of these variation effects. The result is a flow that achieves prevention, analysis, and optimization of the physical design right up to the signoff stage. The revamped technology lineup in Encounter aims squarely at the 45-nm process node (view the diagram here).

To its Nanoroute router, Cadence is adding what it calls Aura, a fast lithography estimation tool that allows the router to comprehend the lithography impact of particular patterns. As it routes the chip, the router is able to avoid those patterns known to cause lithography violations that won’t print well in silicon. Cadence claims that Aura adds no impact on speed of the router while reducing lithography errors from 60 to 80%.

Tied to the router is a pair of lithography-analysis tools. The first, called the Cadence Litho Physical Analyzer, marks the rebranding of Clear Shape Technology’s InShape product that came with Cadence’s acquisition of that DFM vendor in August. The tool takes stock of the physical geometries in the design and calculates the contours for this geometry when actually printed on silicon. Those contours are used to drive the optimization engine.

The third element is another lithography-analysis tool from the Clear Shape stable. Formerly known as OutPerform, the Cadence Litho Electrical Analyzer tool covers the electrical side of the analysis coin. It also extracts contours for the printed geometries and feeds them into timing and power analysis engines.

Fourth on the list is another tool, known as the CMP Predictor, that came to Cadence via acquisition, this time through Presagus. Cadence spent a year turning Presagus technology into a viable product, calibrating process models across all 65-nm foundries and IDM fabrication lines worldwide (45-nm models are in the testing stage). With the exception of TSMC, which provides its own models, CMP Predictor is the only tool of its kind qualified at all foundries.

The tool takes in the geometries associated with the design as well as the process models calibrated with the actual foundry to which it’s destined. For that process, the models tell the tool that the thickness variation due to CMP will be of a given value. Further, it looks not only at a layer-by-layer view, but also at the metal-layer stack to determine whether the aggregate variation in a given spot on the chip will cause copper pooling.

“This is an area in which we got feedback on rule-based approaches, which leads to overmargin,” says Mike McAweeney, Cadence’s vice president of DFM marketing. “You can end up with systematic yield limiters that you couldn’t find by relying on rules, because rules treat layers individually.”

There are two primary use models for CMP Predictor: prediction of copper “hills” and “valleys,” and finding hotspots. The tool’s results drive intelligent metal fill, which chooses the optimum shape and amount of metal for a given area. What often passes for an alternative is a “metal-everywhere” approach, which carries a significant downside in the form of increased coupling capacitance.

Copper hills and valleys can also have detrimental effects on interconnect shapes and thicknesses. CMP Predictor feeds the thickness data based on the process models into extraction, which yields better timing analysis that accounts for CMP erosion. The alternative here is to add timing margin, which can complicate design closure.

Last on the list of Encounter enhancements is Encounter Timing System GXL, Cadence’s entry into the statistical static-timing analysis (SSTA) arena. The tool avoids the pessimism associated with corner-based timing signoff, and executes its runs much faster than static timing analyzers. The tool has already seen certification from 90 nm down to 45 nm at TSMC, Japan’s Semiconductor Technology Academic Research Center (STARC), and several IDMs. Furthermore, the Cadence Litho Physical Analyzer, CMP Predictor, and Encounter Timing System GXL are included in TSMC’s 8.0 Reference Flow.

For pricing and delivery information on the enhanced Encounter design flow, contact Cadence directly.

Cadence Design Systems


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