Electronic Design

More On Power, ESL, And DFM

The three-headed monster of ESL, power optimization, and DFM continues to dominate discussions with EDA vendors here at the 43rd DAC in San Francisco’s Moscone Center. All three of these technologies are being termed “crucial” for the transition to 65-nm mainstream processes. But a number of competing methodologies continue to battle for the hearts and minds of design engineers.

Whether or not you thought the world needed another C-to-RTL compiler, along comes CebaTech, a New Jersey-based startup that’s poised to compete with Mentor Graphics’ Catapult C for a piece of the ESL marketplace. CebaTech is positioning itself as both a provider of Internet-protocol IP and EDA tools. The IP portion will come initially in the form of a TCP/IP transport offload engine as well as other cores based on the OpenBDS stack, all scalable to 10 Gb/s and beyond. What may be of broader interest are the company’s plans to make a commercial offering of the compiler that made that piece of IP a reality.

Slated for launch in September, CebaTech’s C2R Compiler takes in untimed, standard ANSI C code. From that code, the tool generates cycle-accurate C and synthesizable Verilog RTL. Because the tool generates a cycle-accurate C version of the original source code, users gain the advantage of a pure, native C software environment for debugging and verification.

Another advantage CebaTech is claiming for its compiler is capacity that outstrips that of Mentor’s tool as well as others on the market. According to CebaTech, there’s no limit on the size of C source-code input files that the compiler can handle. That would position the tool for handling full-chip designs as well as block-level IP.

There’s been a plethora of announcements in the power-optimization arena at this DAC. Golden Gate Technology, while not making any new technology announcements, is crowing about customer successes (OKI, eASIC, and Lightspeed) with its Power Gold tool. Basically, Power Gold looks for ways to cut wire capacitance, and then to optimize the gates driving those wires. Theoretically, you get power savings from the lowered capacitance alone, and then another savings from being able to downsize the drivers. There’s also leakage-power gains to be had, as well as placement optimization, which also is based on switching activity.

The tool directs the router in your implementation flow to isolate wires that are handing heavy switching loads, thereby lowering their wire-to-wire capacitances. These “isolation directives” from Power Gold to the router (Cadence, Synopsys, or Magma) can be thought of as “soft constraints” that can be overridden by the detailed router if they run the risk of causing signal-integrity issues.

Power Gold is proven at 130 and 90 nm; Golden Gate is working to finish up a version for 65-nm designs. For the existing version, a 500-kgate design takes about a day to run.

With momentum building for the SystemVerilog standard (particularly on the verification side of the language), Synopsys is helping to build out the SystemVerilog infrastructure through its donation of a library of advanced assertion checkers to Accellera. Defined in the ARM-Synopsys Verification Methodology Manual for SystemVerilog (now available in Japanese; look for a Chinese-language version), the checker library comprises 20 unique assertion checkers. The collection is fully complementary to Accellera’s current Open Verification Library (OVL) of assertion monitors. The checkers correspond directly to widely used design elements such as arbiters, FIFOs, memories, registers, and handshake interfaces.

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