In the VeriasHDL multi-language, single-kernel simulator, designers will also gain a compiler for VHDL-AMS, the recently approved analog, mixed-signal and mixed-technology extensions to VHDL (IEEE Standard 1076.1-1999). VeriasHDL is the first product component in the company’s TheHDL open simulation environment for electronics design. It’s also claimed as the industry’s first simulator for the VHDL-AMS language, as well as the first single-kernel, language-aware simulator. VeriasHDL was created from the ground up to provide interoperability for future model libraries and hardware description languages (including Verilog, VHDL, Verilog-AMS, MAST, Spice and VHDL-AMS). The simulator is said to be the only single-kernel tool to provide the full range of system, behavioral, digital and analog capabilities required to meet the needs of mixed-signal design and simulation. By adopting a single-kernel approach, designers can avoid the costly and cumbersome use of analog and digital simulation engines loosely coupled via backplane or analog/digital co-simulation technology. The single kernel efficiently provides solutions for both analog and digital parts of a design and keeps them fully synchronized using the firm’s patented Calaveras algorithm in much the same way that its Saber simulator does. VeriasHDL has also been designed to support new languages and standards as they emerge.VeriasHDL is encapsulated within an open architecture with interface specifications being published by the firm. The interfaces include Advanced Intermediate Representation with Extensibility (AIRE), which decouples the language compilers from VeriasHDL to enable industry re-use of compiler technology.