I ’ve been covering the EDA industry full-time now for seven years this month, and I had been covering it at least part of the time for three or four years before that. Looking back, I cannot remember when it wasn’t said that “verification takes up 70% of the design cycle.” Can you?
Assuming that the old bromide is true, consider the pressure on those designers who must exhaustively prove that a design works as intended in all use modes and under all conditions. In baseball, batters are considered successful when they fail in their mission 70% of the time.
Imagine the consequences for verification engineers who fail to catch 70% of the bugs in a design! Rather, verification teams must perform as near to perfection as possible with shrinking resources, even as the designs they’re ironing out grow larger and more complex.
More E&P for D&V
For design and verification teams, the answer must come in the form of greater efficiency and productivity. That’s where the EDA industry purports to head in 2008 with tools and methodologies that increase the level of automation as well as abstraction.
Movement toward greater interoperability among tools and flows will be a big part of making verification more efficient in 2008. Some of the biggest time-wasters in verification arise simply because the vendors’ simulators and verification methodologies are so disparate that testbenches must be rewritten when designers want to use multiple simulators.
This year’s launch of the Open Verification Methodology (OVM) for SystemVerilog is a step in the right direction. It comprises a methodology and a library of class-based building blocks already supported by multiple EDA, intellectualproperty (IP), services, and training providers.
Source code is available so library and OVM-compliant code can be easily run on new simulators. The OVM is a hopeful indicator of further cooperation to come between EDA vendors that mutually benefits both them and the engineering community.
In a similar spirit of cooperation, we’ll enjoy more collaboration in 2008 between EDA standards groups. This is critical, as the development of complex systems-on-a-chip (SoCs) generally involves the use of IP written in multiple hardware description languages (HDLs) that must work interoperably. Thus, the “datasheets” for this heterogeneous IP have to be captured in a standard format—as must the results of this IP integration.
It’s only through cooperation between multiple standards groups that such heterogeneous IP can be successfully integrated. Accellera has been the breeding ground for multiple HDLs, including SystemVerilog, while the Open SystemC Initiative (OSCI) has developed SystemC. IP written in these and other languages is increasingly found within the same platform designs, and it must be able to be used interoperably.
Furthermore, the SPIRIT Consortium is developing the IP-XACT standard for capturing metadata for both IP blocks and the platforms that result from IP integration. Clearly, since IP-XACT will capture metadata about IP written in languages that are developed within Accellera and OSCI, there is a need for all these groups to work in close coordination.
The growing trend toward power-aware design has brought such techniques as clock gating and multi-threshold CMOS (MTCMOS) into the mainstream. But more advanced power-management design techniques such as power gating, multivoltage domains, and dynamic voltage/frequency scaling (DVFS) will be required to meet tight power budgets in the coming months and years (see the figure). These techniques have major impacts on the overall design flow, including verification.
Static and dynamic functional verification tools will need to advance to accurately handle supply voltage as a functional input. Simple x-propagation techniques will prove to be inadequate, and more sophisticated multivoltage analysis and voltage-aware simulation will be necessary.