Electronic Design

In Nanometer IC Design, Accurate Wiring Details Hold The Key To Success

One characteristic of the evolution of digital chip design methodology is that new silicon generations require new EDA technologies but rarely abandon old ones. In deep-submicron designs, engineers performed timing closure with cell placement instead of during RTL synthesis, as they had previously.

Yet RTL synthesis was (and is) still necessary. The new placement-based optimization tools, including physical synthesis, added to the technology base. The change was in using RTL synthesis to make good netlists rather than to close timing.

A similar dynamic is in effect as the industry moves into the nanometer era. At all submicron geometries, wiring delay dominates timing. At 130 nm and especially at 90 nm, most of the capacitance on a wire no longer comes from its own topology, which can be estimated from placement. It comes from its relationship with surrounding wires (lateral capacitance) and specific signals on those wires. This depends on routing.

Wiring delay is fundamental to nanometer design. For new nanometer technologies, the old submicron methodologies of post-route timing and manual signal-integrity repair require a stretch. Multiple closures are necessary because chip timing before and after routing (where wires are created) don't match. Pre-routing timing estimates aren't accurate at nanometer geometries. Just as submicron placement problems were solved with actual placement information instead of estimates, methodologies that solve the nanometer problem will use actual routing information, not estimates.

Nanometer design methodology begins with a complete chip design representation, including routed wires, called a silicon virtual prototype (SVP). The SVP lets designers accurately determine chip performance, including timing and congestion, and create a guideline for its implementation. SVPs are close enough to tape-out quality that the design team can accurately assess any physical aspect of the chip. SVPs can be created and updated fast enough to enable frequent full-chip builds. A fully detailed layout with all wiring is the only guarantee that all aspects of the design are correct simultaneously. As the design progresses, the designers systematically refine the SVP toward final implementation.

Besides methodology, new tools must augment old ones. Chief among these are automated optimization tools that account for routing to save the design schedule from extensive manual repair of timing and signal integrity. Just as submicron placement tools brought in some synthesis technology, nanometer routing tools integrate analysis and optimization technology. A pairing of wire-based design methodologies and automated design closure tools based on routing, not placement, will win over stretched versions of older approaches.

As with earlier design shifts, submicron-era tools such as physical synthesis will remain keys to nanometer design. But their roles will change in ways designers may not expect. The real focus, as before, is on how much time and stretch it takes to complete chips. This is where the impact of new methodologies combined with new and old tools will be measured and where successful teams will distinguish themselves.

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