In moving to nanometer process technologies at 130 nm and below, semiconductor designers face a variety of physical and electrical effects that can significantly degrade circuit performance. For these nanometer designs, traditional corrections applied after tapeout are simply ineffective, requiring more broadly based development strategies.
With nanometer processes, silicon success depends on the designer's ability to anticipate manufacturing concerns before tapeout. To achieve acceptable yield (or even working silicon), designers must address the impact of manufacturing- and lithography-based distortions of wires, dielectrics, and devices using design-stage simulations and timing-analysis techniques that are more accurate.
The solution lies in deploying a range of improved design-stage capabilities, including better device characterization; higher-accuracy extraction; and improved analyses for power, signal integrity (SI), and electromigration analysis-as well as reticle design and wafer-layout solutions. By applying manufacturing-aware tools and methods throughout design, semiconductor companies can enhance nanometer yield by anticipating manufacturing effects earlier and more effectively.
Market demand continues to accelerate IC design requirements toward greater functionality, higher clock speeds, and lower power requirements. In response, silicon foundries are delivering sophisticated manufacturing technologies that combine sub-wavelength geometries with such advances as copper interconnect and low-k dielectrics. The designer's ability to exploit these manufacturing technologies results in larger, more complex ICs that exhibit increased nanometer-related effects and lower yield.
Each new generation of process technology has complicated IC manufacturers' ability to achieve acceptable silicon performance (Fig. 1). At 0.18 mm and larger geometries, design yield was predictable and within acceptable margins. Designers worked with a relatively stable set of process metrics, relying on manufacturing to find incremental yield improvements as designs ramped to volume production.
In turn, the post-design ramp-to-volume production was relatively steep (Fig. 2a). When yield dropped below expected levels, engineers could likely fix problems after tapeout. As process geometries shrink below 130 nm, however, semiconductor designers face greater difficulty in achieving predictable silicon performance. Therefore, actual yield remains flat in the early stages of production ramp-up (Fig. 2b). In fact, manufacturers find that only slightly more than 40% of nanometer designs operate as expected, and 60% need a complete mask re-spin to achieve acceptable yield and performance.
At nanometer geometries, leakage currents become significant, increasing overall power dissipation. Also, lower supply voltages used with fine-line geometries mean lower noise margins and more sources of SI problems. Higher-frequency signals in nanometer wires increase the SI impact of crosstalk and coupling on circuit timing and function as well. Furthermore, at 500 MHz and above, clock and signal paths can take on distinctively analog behavior, requiring digital designers to adopt methods that were once largely the exclusive domain of analog engineers.
As clock rates continue to rise, designers need to further tighten design parameters to meet chip performance requirements, resulting in longer design cycles. At the same time, tight packing of fine-line features complicates accurate modeling, so simulated results diverge more radically from actual silicon performance.
Shrinking features mean engineers must face greater difficulty in accounting for statistical device-parameter variations, because device parametric variation and process standard deviations generally increase. To account for this greater variation, designers need to adopt more effective "design-centering" techniques. Moreover, they've got to apply robust design techniques, such as via redundancy and metal fill, that don't otherwise directly contribute to design function.
Conventional development methods are less effective for improving yield in modern processes because traditional process-related yield issues no longer strictly dominate yield. At nanometer process nodes, performance and lithography issues begin to exert a more pronounced influence (Fig. 3). As a result, the pursuit of enhanced yield now involves a broader agenda beyond conventional design-for-manufacturing (DFM) efforts, such as design-rule checking (DRC), Optical Proximity Correction (OPC), and fracturing.
Companies can no longer afford to let design engineers throw designs "over the wall" to manufacturing and trust that manufacturing will optimize yield. Instead, to achieve effective yield-enhancement strategies, designers must consider manufacturing yield and DFM issues throughout the design cycle, using integrated tool suites that help them design complex devices with yield in mind. Indeed, engineers need to account for these concerns in each of the three phases of yield enhancement to improve first silicon, boost the ramp-to-volume, and improve profitability in volume production (Fig. 4).
Enhancing First Silicon
As part of their efforts, engineers begin to enhance yield by using yield-optimized library cells and optimized hard-silicon IP cores. Manufacturers often pre-qualify cell libraries for a target process, including such features as antenna diodes in flip-flops to enforce antenna design rules. But beyond implementing improved design techniques, improving yield in nanometer designs depends increasingly on improved design centering, more accurate parasitic extraction, reliable analysis of power and SI effects, and using design recommendations from silicon foundries.
At nanometer geometries, natural manufacturing variations can affect device performance, particularly in analog, mixed-signal, and radio-frequency (RF) designs. These ICs are particularly sensitive to process variations, including lot-to-lot variations, chip-to-chip variations, and variations across an individual die.
Design-centering techniques help engineers minimize yield loss due to these variations. Here, newer tools help designers synthesize the correct device geometries to meet specifications at the center of process-parameter spreads. For example, if analysis shows that a design would exhibit a low yield, engineers can apply automatic design-centering methods. They would add statistical corners to the design's goals and optimize feature sizes until the design is centered within the likely ranges of manufacturing effects (Fig. 5).
With previous process generations, designers could protect designs from manufacturing-related variations by widening margins in timing and in physical layout. Yet at advanced technology nodes, the impact of nanometer effects can exceed reasonable margins, resulting in nonfunctional first silicon and costly diagnostic efforts to unravel the sources of failure.
While the use of margins has helped ensure working first silicon, designers inevitably sacrificed other performance criteria or die area by broadly increasing margins. Unfortunately, they lacked the precise data needed to determine specifically the necessary margins. Furthermore, this approach can actually lengthen the design cycle and inevitably lead to the use of larger buffers, more power dissipation and heat, greater risk of SI and electromigration problems, and increased chip area.
Luckily, accurate parasitic extraction supplies the detailed data needed to reduce margins, even in the face of manufacturing variations in advanced process technologies (Fig. 6). Today's more accurate extraction tools can account for systematic process distortions, minimizing the need for excess margins and problems related to over-design.
In fact, accurate parasitic extraction becomes critical when advanced manufacturing methods introduce performance variations in individual wires. For instance, using copper interconnect leads to individual variations because chemical mechanical polishing (CMP) can wear down the tops of copper wires, which are softer than the surrounding insulating dielectric.
CMP can result in wires with uneven copper thickness across a chip. In turn, this thickness variation causes variable interconnect sheet resistance and capacitance across the chip, leading to variable parasitic delay-even for wires of equal length. For nanometer technologies, this delay variation can result in serious discrepancies between timing simulations and silicon performance.
To reduce these CMP effects, manufacturers insert "dummy" metal to increase copper uniformity across a chip. For the designer, the challenge is ensuring that dummy metal insertion has minimal impact on signal wire resistance due to metal density and on wire capacitance due to coupling.
To ensure high chip performance and yield with today's chip-design complexity, accurate and detailed parasitic RLCK extraction is critical for simulation and analysis. Advanced extraction tools provide accurate 2D and 3D modeling and characterization of advanced dielectrics, trapezoidal conductors, copper technology, and other technologies found in modern processes. With these more accurate extraction tools, designers can account for the manufacturing-related changes in resistance and capacitance. This lets them reduce margins to enhance design performance and yield.
SI And Power Analysis
With the availability of more accurate data and improved analysis methods, designers are more carefully examining the growing impact of IR drop and SI on yield in nanometer design sign-off (see "Power Analysis Plays Key Sign-Off Role,"ED Online ). Advanced SI tools can accurately determine the effects of noise on timing and function in complex designs. With these tools, designers can isolate victim nets exhibiting low noise immunity, avoiding potential noise-related silicon failures well before tapeout.
Power analysis has also earned greater attention in nanometer design flows. IR drop across large devices can introduce both setup- and hold-time violations, which ultimately will reduce performance yield (Fig. 7). If IR drop affects the clock network, the clock is delayed, potentially resulting in hold-time violations. Conversely, if IR drop impacts a signal net, the signal is delayed and results in setup-time violations.
In the past, engineers attempted to identify IR drop problems by applying a single derating factor to supply voltage across the entire chip. But running static timing analysis with simple derated power can't show additional setup- or hold-time violations caused by IR-drop-related slew variations. This is because the uniform derating applies equally to all of the design's nets.
Designers can only identify these additional violations by including instance-based operating voltages in the static-timing-analysis flow, where each instance is analyzed against its own unique operating conditions. Now more advanced SI tools can use this instance detail to calculate path delays more accurately by including the effects of both IR drop and SI problems in the same calculation.
Emerging power-grid sign-off methods use a combination of static and dynamic approaches for comprehensive power-integrity verification. Here, engineers employ static methods to verify operation of the power network. Then dynamic methods are used to optimize nets for transient performance.
Static IR drop analysis helps designers identify global power-routing issues, such as open circuits, lack of routing widths, lack of power straps, missing vias, and missing via arrays. Static analysis also is the preferred approach for power-electromigration verification because it reliably reveals the results of a design operating over an extended period of time.
Dynamic analysis reports IR drop transients on the power networks, typically caused by localized simultaneous switching of devices. Advanced tools can report the density and efficiency of decoupling capacitors in a nanometer design. With these results, designers can identify where decoupling capacitance can be optimized to reduce IR drop transients or lessen leakage.
The emergence of sophisticated optical lithography techniques has extended designers' responsibilities in facilitating a faster ramp-to-volume. Unlike previous process generations, where manufacturing engineers could independently apply mask corrections and optimizations, sub-wavelength lithography used in nanometer processes can distort wafer-imaged structures. This will physically change design layout and alter circuit performance. Designers must anticipate these distortions before tapeout to minimize risk and reduce sensitivity to manufacturing defects.
For nanometer process technologies, particularly at 65 nm and below, the photomask shapes that represent individual on-chip geometries don't transfer accurately onto the wafer due to wavelength diffraction effects. Because the wavelength of the photoresist-exposing light source is longer than the dimensions of some structures being placed on-chip, the transferred images are distorted on the wafers themselves. Other process steps, such as etching and oxide growth, among others, exacerbate the distortion. Without corrective action, inaccurate device-image replication will lead to large yield losses.
Silicon foundries apply reticle-enhancement-technology (RET) methods to deal with diffraction-induced distortions. RET typically comprises two types of corrections: phase-shift masking (PSM) and OPC. These corrections can create smaller geometries for a given wavelength of light as well as reduce on-chip and chip-to-chip parameter variations. With PSM, the light source is split into two phases to avoid interference patterns and increase the wafer's image resolution.
OPC compensates for line shortening, corner rounding, and other distortions caused by features smaller than the wavelength of the exposing light. Here, the OPC technique augments the mask image with additional features that are smaller than the nominal mask design rules. OPC is typically required for more than two-thirds of the layers for 130-nm designs and virtually all layers at 90 nm. Because the added OPC features are smaller than the nominal mask design rules, these features are much more difficult to generate and process. Consequently, indiscriminately using OPC adds significant complexity to the physical database, dramatically increasing tool run-time and delaying time-to-volume.
By adding new lithography-aware tools in design chains, designers can more efficiently account for subwavelength lithographic effects. As engineers design individual cells, these tools can quickly identify where potential problems may later arise in PSM or OPC. Furthermore, passing along information about critical design structures to lithography helps engineers focus OPC to specific regions of a design as well as reduce OPC run times. As these tools move further upstream in the design chain, semiconductor companies will be able to minimize OPC requirements to produce masks of the lowest possible complexity-reducing costs while maximizing device performance and die yield.
In classic development models, yield improvement relies on detailed process analysis and manufacturing diagnosis. Here, engineers carefully monitor the process to determine if it's within nominal specifications, and the foundry fine-tunes the process to the design to achieve maximum yield.
Advanced process-monitoring software arms engineers with a diagnostic environment that lets them more effectively analyze design intent and collate manufacturing information to develop better yield-enhancement solutions. Engineers also may use special failure-analysis equipment to isolate root causes of chip failures, thereby identifying any yield-affecting problems in the chip-fabrication process.
Each yield enhancement in this stage directly contributes to greater profitability, so the ability to achieve maximum yield early in volume production will continue to provide a significant advantage. As a result, semiconductor companies likely will adopt emerging capabilities that tighten the data flow between the factory floor and the design station. By improving the ability to anticipate yield improvements earlier in design, semiconductor companies will achieve maximum profitability for even the most complex nanometer designs.
Enhancing Yield In Design
Nanometer yield enhancement requires a more collaborative approach that involves all participants in the design chain: designers, IP vendors, tool providers, and foundries. Instead of tuning a manufacturing process to each design, semiconductor companies and foundries will need to collaborate more actively to tune each design to the process. In turn, success in nanometer design depends on the ability to deploy a design chain that's attuned to the manufacturing requirements of each specific design.
Indeed, every aspect of product development has an impact on yield. By deploying manufacturing-aware tools and methods early in development, semiconductor companies can anticipate potential problems well before silicon. By addressing yield early and often throughout design, semiconductor companies can achieve faster ramp-to-volume production and profit for complex nanometer designs.