Electronic Design

Network-On-Chip Tools Arrive for The Masses

It’s not enough to call it a “bus” anymore when the bus in question resides on one of today’s insanely complex systems-on-a-chip (SoCs). It’s far more accurate to speak of a “network-on-chip,” or NoC. What better describes the kinds of sprawling top-level interconnects that form the nervous system of high-end chips?

In 2006, Arteris shipped the first commercial NoC product. The company’s NoC Solution targets the design of top-level interconnects in the most complex SoCs. “We’re currently seeing designs of 1 to 1.5 Mgates,” says CEO Charles Janac. To address that complexity, NoC Solution remains the Arteris flagship product, allowing SoC architects to automatically generate intellectual property (IP) for a NoC that handles multiple traffic classes and interconnect types while helping manage power, area, and performance.

Now, Arteris has rolled out extensions to its product line that bring NoC technology to a broader range of design teams. For creation of interconnects on mid-complexity SoCs, there’s FlexNoC, while for bus replacement applications, there’s FlexWay. In both cases, Arteris has scaled down its technology to make it effective for most, if not all, SoC designs. “People who have used our product until now for medium-scale projects have paid penalties in terms of latency and area,” says Janac.

These new offerings eliminate those penalties, says Janac. FlexNoC does so by giving users the choice, on a connection-by-connection basis, of using a standard packet format or a zero-latency packet format to carry protocol information. The choice enables architects to achieve the best possible tradeoff between resource utilization and latency for simple designs and for latency-sensitive blocks. The zero-latency packet format eliminates any penalty involved in the packetization process.

Arteris has implemented zero latency using what it calls its flexible packet format, which enables users to trade off wires against latency (see the figure). Normal signals are first converted into a packetized format, which typically requires some overhead in bus cycles to process the packet header. The tradeoff comes in deciding how many bus cycles you want to spend on that process. “If you choose to use more wires, the payload will be wider,” says Janac. “If performance isn’t important, like for audio, you make the packet payload narrower and it takes more cycles to process the payload.”

The Arteris scheme differs by enabling designers to take the packet header and put it alongside the packet payload so there are no bus cycles wasted on processing that header. As a result, latency becomes zero. “You have to use more wires to accomplish this in other schemes, which results in more routing congestion,” says Janac.

FlexWay can be used as a bus replacement in simple SoC designs. It also can be used to address peripheral connection applications on more complex chips. The product is geared toward conserving wires and silicon area in creating the interconnect.

The Arteris FlexArtist design toolset supports FlexNoC and FlexWay. It also guides the design process starting from capture of a functional specification for the NoC. It takes users through architectural refinement and ends with automatic synthesis of a structural view. Users can then automatically produce RTL and corresponding SystemC models for the interconnect. The tools additionally include automatic functional verification and testbench-generation components.

Arteris

www.arteris.com

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