The grim financial news out of the semiconductor industry in the latter half of 2008 did not help raise hopes that new, more efficient design methods will be high on the list of priorities in 2009. But I am cautiously optimistic that we are at an inflection point, and it will serve as a harbinger of good things to come for the system-on-a-chip (SoC) design community in the new year and beyond.
Design teams realize that nearly everything possible in terms of automating optimization of designs below the register-transfer level (RTL) has essentially been accomplished. Design teams are now looking at using automated solutions during the RTL and system-level design phases. The goal is more efficient use of engineering resources and more optimized design implementations.
This is similar to what happened when logic synthesis tools became a mainstream part of the design flow. Designers relinquished full control of their design schematics and gate-level netlists to tools that could automatically produce higher-quality gate-level designs from an RTL description and accomplish this in significantly less time.
Acknowledging that logic synthesis provided better quality of results faster than manual efforts enabled engineers to give up the notion of understanding every detail of their gate-level designs. It improved design-team efficiency and productivity and dramatically accelerated the design of more complex, higher-performance designs.
This same trend is happening again. Design teams have started to see the excellent results delivered by emerging high-level synthesis (HLS) and automated RTL optimization tools, and they’re relinquishing the need to completely control their RTL design. The availability of mature, formal verification tools to ensure functionality is preserved is a key aspect of the tools’ acceptance.
As confidence grows in the design community, it will translate into the wide adoption of a more efficient design methodology. Using such a methodology, designers need only concern themselves with modeling the required functionality in RTL, C/C++, or SystemC and not with the manual optimization of their RTL.
In the coming year, RTL designers will embrace new tools that will be game changers in terms of engineering team productivity and the level of design optimization that will be achieved. This could signal good things to come in 2009.
TOM SANDOVAL is the chief executive officer of Calypto Design Systems Inc. (www.calypto.com), Santa Clara, Calif.
