EE Product News

New µPs Raise Performance Bar For PowerQUICC Family

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With the introduction of the MPC860 Plus (MPC860P), the performance level of the PowerPC series of QUICC (Quad Integrated Communications Controller) devices has once again been given a major boost. At 80 MHz, the MPC860P PowerQUICC microprocessors offer 106 CPU MIPS (using Dhrystone 2.1) compared to 87 MIPS at 66 MHz for existing MPC860 µPs. The 860P also has a 16-Kbyte instruction cache and 8-Kbyte data cache, quadruple and double, respectively, MPC860's cache figures. Depending on application, the larger cache alone is said to significantly boost system performance. Further, 860P's 8 Kbytes of dual-port RAM provides more space to execute microcode. And of course, 860P processors maintain pin-for-pin compatibility with 860 devices and their 3.3V operation and 5V I/O tolerance, allowing them to be used to enhance existing 860-based designs without modifying the designs.In addition to an embedded PowerPC core, the MPC860P also integrates on-chip: a separate RISC processor for handling communications; four Serial Communication Controllers (SCCs); support for multi-channel HDLC, Ethernet, ATM, and more; SPI and I2C interfaces; and much more. Fast Ethernet will be added to the processor this summer,with MPC860DP, a lower-cost version of 860P having two rather than four SCCs, also scheduled for a summer launch.

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