An EDA company offering electrically-correct design closure software, has announced the availability of its enhanced NoiseIT, a noise detection and correction tool for deep submicron SOC designs. NoiseITÕs new capabilities give cell-based designers better ways to verify and correct for noise on critical nets that are important or have narrow noise margins. This tool serves to improve glitch modeling and propagation characteristics to improve design accuracy. NoiseIT uses finer windowing as compared to typical minimum/maximum static timing techniques to eliminate the pessimism, which causes false errors. This tool also detects and corrects potential data dependent delay problems from cross-talk noise. The electrically-correct tool suites run on Sun workstations. The FormIT integrated analysis, placement and optimization tool for timing closure and convergence and area improvement is priced at $180,000. The optional NoiseIT tool is priced at $105,000.