To achieve signal-integrity design closure for low-power systems-on-a-chip, designers need library views that let them account for the many facets of multivoltage nanometer processes. Cadence Design Systems and Virage Logic have generated and qualified library views that includ Cadence's effective current-source model (ECSM) extensions for accurate supply-voltage delay predictions and noise library views (cdB) for signal-integrity analysis.
When used with Cadence's Encounter digital IC design platform, these library views allow designers to accurately account for crosstalk, supply-voltage (IR) drop, voltage and frequency scaling, and the multiple voltage-island support required for 90- and 65-nm designs.
Virage Logic's IPrima Mobile, a family of application-optimized IP platforms introduced last year, includes STAR single- and dual-port SRAMs, ASAP ultra-low-power memories, ASAP ultra-low-power standard-cell libraries, and Base I/O cells. The standard-cell products now support the cdB noise library views.
The ASAP Memory embedded memory compilers have been enhanced to enable noise-library creation. This is essential to accurately isolate and correct crosstalk-induced failures that may occur at the interface to each memory block.
Cadence's ECSM library format lets designers model delays under different voltage scenarios. In low-power applications that vary the supply voltage for a more effective tradeoff between performance and power consumption, these library views are essential. The views also can be used with Cadence's CeltIC crosstalk analyzer and SignalStorm nanometer delay calculator.Cadence Design Systems
www.cadence.com Virage Logic