High-speed networking applications such as Ethernet switches and backbones are the application domain of a new IC that reportedly integrates on-chip for the first time eight Physical Layer Devices (PHY) and eight Media Access Controllers (MAC). The melding of PHYs and MACs together on-chip, as well as use of a flexible split bus interface and smaller die size will reportedly result in significantly reduced design time and cost for network OEMs. The chip's flexible bus interface is programmable for a 64-, 32- or 16-bit bidirectional or split bus, which supports simultaneous transmission and reception of signals from two ports.
Working at full capacity, the L88800 octal MAC/PHY chip can handle data rates of up to 4.8 Gb/s from all eight of its ports at the same time, allowing up to 24 full-duplex ports to be configured on the same bus. The IC uses an auto-negotiation algorithm for configuring each port to a specific combination of full- or half-duplex, 10- or 100-Mb mode of operation. The device provides flow control for both full- and half-duplex operation. The L88800 comes in a 352-ball enhanced BGA package and costs $40.50 each/50,000.
