What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key phase in the design process that has always been in the crosshairs is timing closure. The length of the timing-closure process may determine if the chip meets a critical market window or not. One of the significant timing closure challenges to users of leading-edge processes is the exponential growth in the number of timing scenarios that must be analyzed in order to achieve working, high-yielding silicon.
Timing analysis at multiple corners is not new—designers have always had to consider worst-case scenarios to ensure that their chips would function across a range of operating conditions. However, the combination of on-chip variation (OCV) at smaller process geometries and the increasing use of multiple voltage domains and different chip operating modes has led to an explosion in the number of operating corners or “scenarios” (see the figure) that must be analyzed. It’s no surprise, then, that timing analysis is rapidly becoming one of the key bottlenecks in the chip design schedule.
STA: GROWING PAINS OR OUT OF GAS?
The average number of scenarios that design teams require for timing verification has increased since the introduction of timing analysis. In 1997, when the current generation of static timing analysis (STA) tools hit the market, design teams were signing off with one to two operating modes and two process-voltage-temperature (PVT) corners. System-on-chip (SoC) design—which entails adding as much functionality onto a chip as possible—has seen a doubling of timing scenarios every two to three years. As designs transitioned to 130 nm and below, incorporation of new functional operating and design-for-test modes became a standard part of timing analysis. And as process technology continues its march of miniaturization, more and more PVT corners have been added to the mix, creating a sprawling matrix of analysis that is required to meet chip timing specifications and timing closure. At 28 nm, it will not be uncommon for some designs to require analysis of more than 200 different scenarios.
To address this explosion in the number of scenarios that must be analyzed, design teams have adopted a somewhat brute-force approach in order to fit this analysis into the project schedule. The approach is simple but expensive: For every timing scenario that must be considered, secure a separate machine and STA license to run that scenario. In essence, the approach is to grow a matrix of STA machines and licenses such that the different scenarios can be run in parallel. Although some STA platforms can run multiple jobs per multi-CPU machine, the STA runtime for today’s designs, and the memory requirements for crosstalk analysis, force designers to allocate only one STA job per machine.
MORE MODES AND CORNERS—TIME FOR SSTA?
In the traditional STA flow, variations in the manufacturing process, such as dopant levels, etchant concentrations, and photo masks used to create the wafers, are captured in the form of PVT corners. Introduced around the 130-nm node, on-chip variation (OCV) analysis was used to add margin to the timing paths to account for the aggregate number of total variations from a wide variety of sources. This technique has been applied to clock and data paths for setup and hold timing checks. By adding timing margin to their design, design teams are stressing timing paths to above and beyond the actual timing specification. With the extra timing margin on the design, variations in the manufacturing process should not adversely affect yields.
Implementing designs with OCV can be very expensive at advanced technology nodes. By applying generic derating values across the chip, performance and area may be adversely affected. For setup timing the maximum frequency may be limited by aggressive setup derating. For hold timing, excessive buffering may be required to meet pessimistic hold margins.
At 40 nm and below it becomes increasingly complicated to capture the number of potential variations in the PVT corners. Before the recent migration to 40 nm, a couple of technologies have emerged to deal with the pessimism associated with OCV. Statistical STA (SSTA) and advanced OCV (AOCV) have lingered on the periphery as potential ways to reduce the pessimism of generic OCV.
SSTA was introduced around the 65-nm node with the intention of adding statistical variation analysis to the traditional STA-based sign-off flows. Using statistically-created libraries, designers would be able to evaluate their design’s susceptibility to variation. At 65 nm, traditional STA signoff continued to produce working silicon using PVT-based sign-off and OCV margins. But at 40 nm and below, design teams are taking another long look at SSTA as a potential solution for improving yields and reducing timing analysis. While most EDA vendors offer an SSTA solution, there has not been that “Hallelujah moment” where the clouds parted, trumpets sounded, and design teams declared, “SSTA will reduce the number of PVT corners and make my sign-off flow better and faster.”
Even though SSTA will likely remain on the periphery of timing flows for the foreseeable future, AOCV analysis has gained some attention because it has the potential to reduce OCV timing margins and thus remove some of the pessimism associated with traditional OCV. While table-based lookups may reduce the pessimism in timing paths, AOCV provides an incremental step between global OCV margins and true statistical analysis based on actual variations. While AOCV does not solve the burden of the growing STA scenario matrix, it does provide design teams a tool to reduce the number of timing fixes per scenario.
WANTED: A SCALABLE MM/MC APPROACH
As the STA multi-mode/multi-corner (MM/MC) or multi-scenario matrix continues to grow, design teams continue to absorb more analysis, using more licenses on bigger machines. With fewer engineers and larger, more complicated chips at the advanced 40- and 28-nm nodes, advances in STA timing tools are required to ensure that the timing closure process does not get bogged down. Recent evolution of design-margining techniques such as AOCV enable design teams to chip away at the pessimism associated with OCV. This will help, but design teams can’t keep asking their management for more STA licenses and hardware for every new chip. That approach does not scale and will not continue to be funded. To meet the timing closure demands for the next generation of chips, design teams will need a major advancement in STA. A new approach is needed that can meet the increasing number of PVT corners and operating modes using existing hardware and without changing the STA flow that designers are already familiar with.