Electronic Design

Open Verification Methodology Relieves Inefficiencies

Since the IEEE’s adoption of SystemVerilog as IEEE Standard 1800-2005, and EDA vendors’ subsequent release of products supporting that standard, the semiconductor verification teams my company serves have been disappointed by the reality of what’s been delivered. But with the recent announcement of the Open Verification Methodology (OVM), all that is about to change.

Some would argue that from the outset, SystemVerilog provided everything a verification engineer would want from a standard language aimed at hardware designs. Under the SystemVerilog umbrella was an object-oriented programming model, constrained-random test generation, assertions, coverage measurement, and advanced data types, to name but a few (view the chart here).

Yet, the biggest potential win was at the business end of the industry. SystemVerilog promised to reduce costs and enhance productivity via project, resource, and infrastructure management improvements.

Verification had been the “long pole in the tent” for a number of years, but the problem grew to consume 60% to 70% of a given development schedule. SystemVerilog promised to level the playing field to open competition, and therefore encourage innovation that would break the “verification bottleneck.” In addition, as this open language gained support from the major EDA vendors, industry observers predicted the emergence of a portable verification environment. As a result, companies like XenoTech Software could provide verification IP (VIP) with an economy of scale created through verification interoperable development, deployment, and reuse.

Where the Standard Left Us

The pros and cons of one verification language over another can be argued, but the major inhibitor to mass adoption of SystemVerilog was where implementation let us down on the latter half of the promise—cross-platform portability and infrastructure cost reduction.

Each EDA vendor’s simulator supported a different class library. Therefore, a testbench or a piece of VIP developed for one simulator in SystemVerilog could not be compiled and run on a simulator from another vendor.

This fundamental incompatibility stressed both sides of the supply-and-demand equation. On one side, the semiconductor vendors were still locked into the simulator they chose, despite the promise of openness in SystemVerilog. On the other side, VIP vendors remained burdened with the cost of producing vendor-specific products to support the adoption of one class library over another. Both sides were locked into disconnected design chains laden with the costs of supporting multiple class libraries.

The result was no real competition, little innovation, and a slowed transition to a promising new point on the verification productivity curve.

What OVM Gives Us

Cadence Design Systems’ and Mentor Graphics’ collaboration to create the Open Verification Methodology (OVM) will deliver on both parts of the SystemVerilog promise for at least two of the three main simulation and verification tool chains. Further, the OVM retains designers’ familiar and complete verification environment, but breaks from the traditional in three important ways (see the figure).

A unified and open-source class library:

Both companies have committed to make available a single SystemVerilog class library in open source. Leveraging the widely accepted Apache 2.0 licensing model, the OVM Class Library license will simply require preservation of the copyright notice and disclaimer regardless of whether users apply it in open or proprietary development. While the process for further development of the library is still to be determined, the intent is to make all advances made by either company interoperable and open.

Simulator interoperability:

In addition to combining the openness of the class library with the ongoing commitment to make their simulators strictly IEEE-1800 compliant and interoperable, Cadence and Mentor are making the verification environment portable and transparent across their simulators. Both companies will also verify OVM interoperability between the Cadence Incisive and Mentor Graphics Questa Verification Platforms. These three points free engineering managers to focus on adopting the methodology, resources, and practicalities of getting a chip out on time instead of wrestling with tool and language incompatibilities.

A single verification-IP development environment:

OVM empowers VIP vendors to invest their resources in a methodology without loading the opportunity costs onto a decision that could make or break the company. Now VIP vendors can focus all of their resources on innovation and provide value through increased productivity, quality, and shorter verification schedules for their customers.

Moreover, OVM ensures interoperability with other higher-level languages, such as SystemC, e, Verilog and VHDL. This key attribute ensures reuse of existing VIP, bus-functional models (BFMs), and test benches as the verification team moves up through system and abstraction hierarchies.

In Summary

The Open Verification Methodology represents an opportunity for SystemVerilog to deliver on its original promise. Verification engineers are supplied with a comprehensive methodology and programming model that’s built on a standard high-level language. All of these are essential to solving complex verification challenges, regardless of the simulator.

Verification IP vendors gain a single methodology with which to compete on innovation, quality, and the reliability of their wares. Verification and project management can focus resources and internal practices on a single environment. And verification flows can be unified across projects and across teams to reduce software and support costs, resulting in the efficiencies throughout the design chain.

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