Electronic Design

Open Verification Methodology Sprouts Hierarchical Guidelines

The latest version of the Open Verification Methodology (OVM) provides a new OVM User Guide, which contains step-by-step guidelines to help users develop reusable, interoperable verification IP and hierarchical environments to facilitate plug-and-play verification. Spearheaded by Mentor Graphics Corp. and Cadence Design Systems, the open-source OVM 2.0 extends the sequential stimulus mechanism in the OVM with transaction-level modeling (TLM) interfaces to improve the modularity and reuse of stimulus sequences. Other enhancements include direct support for parameterized classes in the OVM factory and built-in debug support for TLM connections throughout the hierarchy.

The OVM User Guide provides straightforward documentation on all aspects of the OVM, including an extensive review of TLM for verification, guidelines for developing reusable OVM verification components, instructions for building verification tests, and in-depth discussions on the more advanced features of the OVM. The guide also includes an extensive example showing how to apply these concepts to the creation of a full hierarchical verification environment, including tests that configure the environment and select the desired stimulus sequences to exercise the required functionality.

The Open Verification Methodology, based on the IEEE Std. 1800-2005 SystemVerilog standard, is the industry’s first open, language-interoperable SystemVerilog verification methodology. It provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modeling interfaces. It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.

Cadence Design Systems

Mentor Graphics

OVM World User Community

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