EE Product News

Parametric Design Rule Checker Debuts

VN-Check parametric design rule checker goes to work with Verilog and VHDL IC designs early in the chip development cycle, serving to help identify design bugs as early as possible and facilitates the reuse of existing designs. It is also helps ensure that the design’s hardware description language (HDL) code is portable between different languages and tools, and it also makes the code more readable and better documented for future use. Offered as part of Verification Navigator design verification environment, the checker also provides access to more than 400 built-in design rules for both Verilog and VHDL. The built-in rules include specific checks for synthesis, coding style, documentation, and naming conventions. Another version, VN-Check CRG, also creates the necessary interface code and compiles the user-defined rule into a format readable by VN-Check. List price starts at $15,000 for a single language when bundled with the base configuration of Verification Navigator and $20,000 as astandalone product. VN-Check CRG lists for $45,000.

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