Electronic Design

Parasitic Extraction Tool Targets Next-Generation ICs

Achieving design closure in a system-on-a-chip (SoC) development project generally requires a great deal of patience. SoCs tend to include more and more custom circuitry, which means long simulation runs and some stabs in the dark at something resembling signoff. The combination of more transistors and the need to model more complex parasitic effects can double, if not quadruple, the runtimes of circuit-level simulation.

One way to get around that is to make parasitic extraction faster. That’s what Synopsys has done in its StarRC Custom parasitic extraction suite. The tool unifies the company’s foundation Scan-Band extraction technology and its Raphael NXT fast field solver under one roof. And because it offers tight links to the Synopsys CustomSim circuit simulator, simulation times can be as much as 10 times faster while maintaining signoff accuracy. StarRC Custom also is tightly integrated with the Galaxy Custom Designer implementation tool suite.

Context-specific device parasitics are becoming more critical at smaller geometries. It’s no longer enough to model device parasitics in isolation. In sensitive circuits and critical paths, parameters such as contact-to-gate or contact-to-contact parasitics must be extracted in the device’s layout context. This puts pressure on simulation performance and runtime.

StarRC Custom addresses these issues through its high subfemtofarad accuracy. The Raphael NXT fast field solver goes even further and targets nets in very sensitive analog circuits requiring sub-attofarad accuracy. “One customer is using it to perform extraction of standard cells,” says Robert Hoogenstryd, director of marketing for design analysis and signoff products at Synopsys. The idea there, says Hoogenstryd, is to gain an extremely precise reading of parasitics inside the cell.

Thanks to StarRC Custom’s optimized link with the Custom- Sim circuit simulator, users can tune their extraction runs for high simulation efficiency. “There can be so much variation from device to device that they must be extracted based on the layout and then fed to simulation,” says Hoogenstryd. However, extraction at this level of detail across an entire functional block will make for extremely long simulation runs. Thus, StarRC Custom and CustomSim enable users to focus on critical nets at this level of detail, even critical devices (see the figure, a).

Another extraction-tuning option that’s available to users is active-node extraction (see the figure again, b). In CustomSim, users can capture the activity in specific nets and/or devices and use that data to drive the tuning of StarRC Custom’s extraction. The extraction engine ramps up its accuracy on the high-activity devices and nets to create a parasitic netlist tuned for the simulation.

A third tuned-extraction method is called hierarchical backannotation simulation (see the figure again, c). For this method, the Synopsys StarRC Custom team worked closely with the CustomSim team to ensure that the parasitic netlists produced by StarRC Custom are tuned to take advantage of a CustomSim capability known as PLX.

Parasitic extraction can be run on a design in flat fashion, resulting in a flat netlist with flat parasitics. This plain-vanilla approach puts the onus on the simulator. Another style is to extract parasitics flat but to annotate the parasitics to a hierarchical netlist.

In this case, the extractor works hierarchically, giving up some context-specific accuracy to create a more efficient simulation netlist. What Synopsys has implemented in StarRC Custom is to extract parasitics flat. Custom-Sim reads in those flat parasitics in conjunction with a hierarchical netlist. This technique, according to Hoogenstryd, is the best route. “This gives high accuracy while boosting performance over simulation using hierarchical extraction,” he says.

StarRC Custom provides a common data flow with the Synopsys Galaxy Custom Designer implementation environment. From the Custom Designer layout tool, users can set up extraction and simulation runs and easily bring the results of those runs back into the implementation environment. “This lets us assemble a nice flow in which people can do in-design analysis,” says Hoogenstryd.

StarRC Custom is in limited availability now with general availability planned for December.


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