EE Product News

Partitioning/Synthesis Tool Speeds ASIC Prototyping

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The Certify synthesis and partitioning tool is said to provide a dramatic increase in productivity for designers prototyping large ASICs, especially for multimedia and communication applications. When combined with popular industry emulation and prototyping tools such as Aptix’s System Explorer, Certify provides a complete ASIC prototyping flow. The tool enables System Explorer users to quickly partition and synthesize 1-million-gate-plus system-on-chip designs at the RTL level. Users avoid long, cumbersome iterations at the gate level by taking their full-chip functional RTL into Aptix’s rapid prototyping process. Designers can make modifications and improvements at an early stage in the design process, reducing time to market and quickening iterations.The Certify tool is an advanced RTL partitioning tool combined with an enhanced synthesis engine. Partitioning is done at the RTL level and is based on synthesis estimates of area and connectivity, resulting in much higher productivity than current gate-level partitioning approaches, it’s claimed. In addition, the tool doesn’t require that the original HDL source code be modified for either observability or partitioning reasons. Typically, verification teams building ASIC prototypes are extremely reluctant to modify the HDL source code.

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