Electronic Design

Physical Design Synthesis Steps Up To Nanometer Designs

As 90-nm design starts ramp up, so does the productivity gap in IC implementation. Most of today's tools have very long runtimes that pose obstacles to achieving acceptable quality of results for the largest 90-nm designs. Sierra Design Automation's Pinnacle is a unified physical synthesis and prototyping tool that aims to speed design closure by five to 10 times compared with existing tools.

Existing physical synthesis tools take an iterative approach to analyzing and repairing worst-case critical paths. Pinnacle uses global bottleneck analysis, identifying nodes that are problematic in timing closure rather than paths. Additionally, an analytical optimization engine computes the optimal configuration of gate selection and buffering to speed critical paths. Alternative tools use brute-force, trial-based optimizations that chew up runtime.

Toshiba has used Pinnacle to implement a 6-Mgate design in under nine hours. These results were achieved using a flat design flow on a 32-bit Linux machine. The same design was benchmarked from 65 to 85 hours with other tools.

Pinnacle handles up to 10 Mgates flat and scales to more than 50 Mgates in a hierarchical flow using 64-bit platforms. It can be seamlessly integrated into existing design flows. Also, it includes built-in global and trial routing engines as well as a static timing analysis engine.

The Pinnacle physical synthesis tool is available now with pricing starting at $395,000 for a one-year license.

Sierra Design Automation

TAGS: Toshiba
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