Physical-verification cycle time increases significantly with each new process generation. Rule-deck complexity contributes considerably to this effect. The number of design rules grows rapidly as manufacturers push the limits of their lithographic processes to print feature sizes smaller than the wavelength of light. New rules approximate the complex, model-based, optical-proximity-correction (OPC) algorithms that foundries apply after tapeout to work around the limitations of their optical lithography systems, as well as add predictability to the printing process.
Foundries regularly integrate completely new classes of design rules to their long lists of signoff requirements. Sophisticated density design rules address chemical-mechanical-polishing (CMP) requirements. Intricate metal spacing rules and demanding via requirements address yield and reliability.
In addition, foundries also introduced the concept of forbidden pitches to improve critical dimension uniformity. Antenna rules have grown in complexity due to the ballooning number of metal layers and transistor types. Entirely new sets of recommended rules, while not strictly required for manufacturing handoff, can measurably impact yield. All of these factors conspire to significantly increase the number and complexity of design rules with each new process generation.
Of course, larger design size also contributes significantly to physical-verification cycle time. Feature-size scaling has kept pace with Moore’s Law, boosting the number of transistors by 80% every two years. Power dissipation limitations restrict frequency scaling; therefore, designers typically exploit new processes by integrating multiple functions onto one chip, rather than the going traditional route of pushing up clock frequencies.
Beginning in the late 1990s, physical-verification tools began to implement hierarchical pre-processing as a means to manage the increasing complexity of design-rule checks (DRCs). In such a methodology, a hierarchical pre-processor identifies repeated patterns of cells and polygons in the design. The pre-processor artificially creates a new level of hierarchy around each repeated pattern, so that the DRC tool checks each pattern only once rather than every time it appears in the design. However, lithographic limitations of recent manufacturing processes increased the effective interaction distances between polygons in the design (the so-called “halo effect”). This dramatically reduces partitioning opportunities and, therefore, negates much of the effectiveness of hierarchical pre-processing. Although the benefits of a well-planned hierarchical design remain indisputable, new halo-based rules claim a growing proportion of physical-verification runtime. We anticipate that the hierarchical approach of the current generation of DRC tools will cease to have any significant benefit at the 65-nm process node.
Flat DRC engine performance has leveled off as EDA vendors integrate new approaches and algorithms over the years. Because hierarchical processing is evidently untenable for future process generations, scalable parallel processing is a pragmatic alternative approach. It's able to achieve the dramatic reduction in physical-verification cycle time that is required to deliver high-yielding designs in nanometer processes. Integrating complex, specialized checks as high-performance algorithms in the DRC software (rather than long sequences of primitive commands in the rule deck) eases the adoption of new and recommended rules.
The daunting cost of mask sets for nanometer processes creates additional pressure to detect and correct errors as early as possible in the physical-verification process. Longer physical-verification cycles can delay time-to-market, but incomplete rule checking can reduce yield, degrade reliability, and invalidate functionality. The combination of complex rules, more transistors, and extra levels of wiring presents a formidable challenge to today's physical-verification tools.
But the new generation of scalable physical-verification systems empowers designers to accommodate all of these requirements, without skipping any steps. The new, massively parallel approaches to physical verification boost throughput to the point where design teams can meet rigorous schedule requirements and, simultaneously, address subtle nanometer manufacturing issues that significantly impact yield. Designers can hence broaden the scope of manufacturing checks but stay on schedule. In addition, these new systems deliver an earlier, deeper, more accurate assessment of the impact of design decisions on yield in nanometer process technologies. Thus, designers no longer need to wait days for the minimum set of results that enables design signoff. The new, scalable approach to physical verification greatly enhances the designer's ability to deliver successful high-yielding designs that work on the first mask set—a significant payoff in the age of one billion transistors, one thousand design rules, and million dollar mask sets.