Electronic Design

Physical Verification Suite Tuned For IBM’s 65-nm Design Kits

Advanced device parameter measurement functionality is now available in the Hercules Physical Verification Suite (PVS) from Synopsys. Developed to support the latest release of 65-nm design kits from IBM, this functionality enables IBM foundry customers using the Hercules layout-versus-schematic (LVS) rule files in the kit to easily and accurately correlate device behavior to the IBM process.

These IBM foundry customers also have access to the latest Hercules design rule checking (DRC) as part of the 65-nm design kit release. These files are qualified for accuracy and optimized for performance.

As device geometries continue to shrink to 65 nm and smaller, circuit performance is improved by changing transistor behavior through the application of special process layers. However, the presence of these layers increases the complexity of measuring device parameters such as speed, power, and area during physical verification due to the number of complex calculations involved. IBM and Synopsys have collaborated to deliver the algorithms necessary to support these new requirements. This entailed adding more device measurement commands to Hercules PVS. These new Hercules commands, which are fed into IBM’s proprietary calculations, deliver greater accuracy so customers can better understand design performance at 65 nm.

The new capability for Hercules PVS is available now.

For more information, visit http://www.synopsys.com

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