EE Product News

Pocatello, ID

Pocatello, ID-A design service that is said to dramatically increase first-time design success of deep sub-micron ASICs, enhance timing performance, and cut delivery times by as much as 60% has been instituted by American Microsystems Inc. The firm's roadmap for timing convergence includes a design flow that integrates the following three methodologies: timing-driven physical layout, clock-tree synthesis, and floor planning. In the design flow, customers synthesize the device using Synopsys tools and create timing constraints and a boundary conditions file. From there, the firm uses the timing constraints and boundary conditions to drive the physical layout to optimize timing performance using the Avant! place-and-route tools. Post placement optimizations include buffer resizing or buffer insertion to fine tune the design timing. Finally, clock tree synthesis is used to place the clock drivers. The result is reported to be improved performance, reduced gate count, lower power and greater opportunities for first-time design success.

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