Electronic Design
A Positive Report from EDSFair

A Positive Report from EDSFair

EDSFair, which takes place in late January in Japan, is one of the first industry events each year and helps provide a glimpse into what the electronic design automation (EDA) industry can expect. This year was no exception. I believe it offered some hopeful signs and pointed toward some positive trends that should surface in 2010.

As EDSFair attendees can attest, design challenges are getting more complex as software becomes a key product differentiator, time-to-market pressures close in, and design sizes reach one billion ASIC gates (see the figure). Given the right mindset, each of these challenges offer great opportunities for EDA.

Over two days, the EVE team met with quite a few of the attendees and was rewarded with a wealth of great feedback on chip design and verification trends in Japan. Not surprising, the Verilog hardware description language (HDL) holds fast to being the number-one language for both ASIC and testbench design. Similarly, simulation is still heavily entrenched in the design and verification flow, despite exaggerated reports of simulation’s demise.

Close to 70% of the attendees we talked to noted that their overall satisfaction level with their verification flow was high. Most encouraging, they all appear to have budgets for verification tools and plan to purchase them within the next six to 12 months.

Perhaps the best news coming out of EDSFair is the evident move to hardware/software co-verification due in large measure to the increased quantity of embedded software content. This well-regarded and efficient design strategy has finally reached maturity and is being adopted by the mainstream after being practice by the innovators and early adopters for many years. Moreover, hardware/software co-verification is a must-implement design strategy as the system-on-chip (SoC) methodology combines software and hardware to form a complete system.

Today’s emulation platform is the natural choice for a hardware/software co-verification strategy because project teams implementing SoCs can use it to simultaneously verify the correctness of both hardware and embedded software. Emulation can process billions of verification cycles at high speeds in a short period of time. Pricing for emulation systems is more competitive, especially noteworthy as software continues to drive up the design costs.

These hearty tools are developing a reputation for their ability to debug complicated multi-layered hardware and for testing the integration of hardware and the embedded software within SoCs ahead of first silicon. They also enable a working prototype for software development in advance of silicon. Equally, emulators give joint hardware and software teams with different skills and problem-solving approaches a way to effectively work together and communicate with one another.

The upbeat news out of Japan on the widespread adoption of hardware/software co-verification portends good things for EDA’s verification sector in 2010. I see further signs of positive trends in other parts of the world, which tells me that EDA is bouncing back after 2009, a bad year for all of us in this market segment. Because there is resurgence in the semiconductor industry, and with it, increased demand for design automation and verification tools, 2010 should be a good year for EDA.

Hide comments

Comments

  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.
Publish