Electronic Design

Post-Layout IC Analysis Tool Nails Down Nanometer Effects

In the implementation phase of nanometer system-on-a-chip (SoC) designs, gate-level analysis serves the synthesis-driven segments. But at some point, designers must delve into full-chip, transistor-level analysis. Then they can smoke out physical effects such as IR drop, ground bounce, electromigration, crosstalk, glitch power, and other pernicious physical effects.

To that end, Nassda's HSIMplus platform bundles version 5.0 of the HSIM simulator with a suite of eight options. These options provide an array of post-layout analyses to address signal integrity and the reliability of signal and power networks in ICs designed for processes at 130 nm and below.

For example, the power-network reliability option offers dynamic voltage-drop and electromigration analysis. The former shows how timing and functional errors are caused by supply-voltage variation. The latter indicates how quickly circuit traces deteriorate due to the density of current flows.

HSIMplus supports compilation of Open Verilog International standard Verilog-A, which describes components using analog behavioral models. Moving to the higher level of abstraction of Verilog-A can speed simulation and verification.

Prices start at $85,000 for HSIMplus and $25,000 for HSIMplus options. Availability begins in April.

Nassda Corp.

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